LMD18245_06 Datasheet, PDF (4/21 Pages) National Semiconductor (TI) – 3A, 55V DMOS Full-Bridge Motor Driver

Electrical Characteristics (Note 2) (Continued)
The following specifications apply for V_CC = +42V, unless otherwise stated. Boldface limits apply over the operating tem-
perature range, −40˚C ≤ T_J ≤ +125˚C. All other limits apply for T_A = T_J = 25˚C.
Symbol
Parameter
Conditions
Typical
Limit
Units
(Note 5)
(Note 5)
(Limits)
CURRENT SENSE AMPLIFIER
Current Sense Offset
I_LOAD = 0A
5
µA
20
µA (max)
DIGITAL-TO-ANALOG CONVERTER (DAC)
Resolution
4
Bits (min)
Monotonicity
4
Bits (min)
Total Unadjusted Error
0.125
0.25
LSB (max)
0.5
LSB (max)
Propagation Delay
50
ns
I_REF
DAC REF Input Current
DAC REF = +5V
−0.5
µA
±10
µA (max)
COMPARATOR AND MONOSTABLE
Comparator High Output Level
6.27
V
Comparator Low Output Level
88
mV
Comparator Output Current
Source
0.2
mA
Sink
3.2
mA
t_DELAY
Monostable Turn OFF Delay
(Note 8)
1.2
µs
2.0
µs (max)
PROTECTION AND PACKAGE THERMAL RESISTANCES
Undervoltage Lockout, V_CC
5
V (min)
8
V (max)
T_JSD
Shutdown Temperature, T_J
Package Thermal Resistances
155
˚C
θ_JC
Junction-to-Case, TO-220
θ_JA
Junction-to-Ambient, TO-220
LOGIC INPUTS
1.5
˚C/W
35
˚C/W
V_IL
Low Level Input Voltage
−0.1
V (min)
0.8
V (max)
V_IH
High Level Input Voltage
2
V (min)
12
V (max)
I_IN
Input Current
V_IN = 0V or 12V
±10
µA (max)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Electrical specifications do not apply when operating the device
outside the rated Operating Conditions.
Note 2: Unless otherwise stated, load currents are pulses with widths less than 2 ms and duty cycles less than 5%.
Note 3: The maximum allowable power dissipation at any ambient temperature is P_Max = (125 − T_A)/θ_JA, where 125˚C is the maximum junction temperature for
operation, T_A is the ambient temperature in ˚C, and θ_JAis the junction-to-ambient thermal resistance in ˚C/W. Exceeding P_max voids the Electrical Specifications by
forcing T_Jabove 125˚C. If the junction temperature exceeds 155˚C, internal circuitry disables the power bridge. When a heatsink is used, θ_JAis the sum of the
junction-to-case thermal resistance of the package, θ_JC, and the case-to-ambient thermal resistance of the heatsink.
Note 4: ESD rating is based on the human body model of 100 pF discharged through a 1.5 kΩ resistor. M1, M2, M3 and M4, pins 8, 7, 6 and 4 are protected to
800V.
Note 5: All limits are 100% production tested at 25˚C. Temperature extreme limits are guaranteed via correlation using accepted SQC (Statistical Quality Control)
methods. All limits are used to calculate AOQL (Average Outgoing Quality Level). Typicals are at T_J = 25˚C and represent the most likely parametric norm.
Note 6: Asymmetric turn OFF and ON delay times and switching times ensure a switch turns OFF before the other switch in the same half H-bridge begins to turn
ON (preventing momentary short circuits between the power supply and ground). The transitional period during which both switches are OFF is commonly referred
to as the dead band.
Note 7: (I_LOAD, I_SENSE) data points are taken for load currents of 0.5A, 1A, 2A and 3A. The current sense gain is specified as I_SENSE/I_LOAD for the 1A data point.
The current sense linearity is specified as the slope of the line between the 0.5A and 1A data points minus the slope of the line between the 2A and 3A data points
all divided by the slope of the line between the 0.5A and 1A data points.
Note 8: Turn OFF delay, t_DELAY, is defined as the time from the voltage at the output of the current sense amplifier reaching the DAC output voltage to the lower
DMOS switch beginning to turn OFF. With V_CC = 32V, DIRECTION high, and 200Ω connected between OUT1 and V_CC, the voltage at RC is increased from 0V to
5V at 1.2V/µs, and t_DELAY is measured as the time from the voltage at RC reaching 2V to the time the voltage at OUT 1 reaches 3V.
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