DS91M040 Datasheet, PDF (4/16 Pages) National Semiconductor (TI) – 125 MHz Quad M-LVDS Transceiver

Absolute Maximum Ratings (Note 4)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Power Supply Voltage
−0.3V to +4V
LVCMOS Input Voltage
LVCMOS Output Voltage
M-LVDS I/O Voltage
−0.3V to (V_DD + 0.3V)
−0.3V to (V_DD + 0.3V)
−5.5V to +5.5V
M-LVDS Output Short Circuit
Current Duration
Continuous
Junction Temperature
+140°C
Storage Temperature Range
−65°C to +150°C
Lead Temperature Range
Soldering (4 sec.)
+260°C
Maximum Package Power Dissipation @ +25°C
SQ Package
833 mW
Derate SQ Package
6.67 mW/°C above +25°C
Package Thermal Resistance
 θ_JA
 θ_JC
+150°C/W
+63.8°C/W
ESD Susceptibility
HBM (Note 1)
MM (Note 2)
CDM (Note 3)
≥8 kV
≥250V
≥1250V
Note 1: Human Body Model, applicable std. JESD22-A114C
Note 2: Machine Model, applicable std. JESD22-A115-A
Note 3: Field Induced Charge Device Model, applicable std.
JESD22-C101-C
Recommended Operating
Conditions
Min Typ Max Units
Supply Voltage, V_DD
Voltage at Any Bus Terminal
3.0 3.3 3.6 V
−1.4
+3.8 V
 (Separate or Common-Mode)
Differential Input Voltage V_ID
LVTTL Input Voltage High V_IH 2.0
LVTTL Input Voltage Low V_IL
0
Operating Free Air
2.4 V
V_DD V
0.8 V
Temperature T_A
−40 +25 +85 °C
DC Electrical Characteristics (Notes 5, 6, 7, 9)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min Typ Max Units
M-LVDS Driver
|V_AB|
ΔV_AB
Differential output voltage magnitude
Change in differential output voltage magnitude
between logic states
R_L = 50Ω, C_L = 5 pF
Figures 2, 4
480
650 mV
−50 0 +50 mV
V_OS(SS)
|ΔV_OS(SS)|
Steady-state common-mode output voltage
Change in steady-state common-mode output
voltage between logic states
R_L = 50Ω, C_L = 5 pF
Figures 2, 3
0.3 1.6 2.1
V
0
+50 mV
V_A(OC)
V_B(OC)
V_P(H)
Maximum steady-state open-circuit output voltage
Maximum steady-state open-circuit output voltage
Voltage overshoot, low-to-high level output
(Note 12)
V_P(L)
Voltage overshoot, high-to-low level output
(Note 12)
I_IH
High-level input current (LVTTL inputs)
I_IL
Low-level input current (LVTTL inputs)
V_CL
Input Clamp Voltage (LVTTL inputs)
I_OS
Differential short-circuit output current (Note 8)
M-LVDS Receiver
Figure 5
R_L = 50Ω, C_L = 5pF, C_D = 0.5 pF
Figures 7, 8
V_IH = 2.0V
V_IL = 0.8V
I_IN = -18 mA
Figure 6
0
0
−0.2V_S
S
-15
-15
-1.5
-43
2.4
V
2.4
V
1.2V_SS V
V
15
μA
15
μA
V
43 mA
V_IT+
Positive-going differential input voltage threshold See Function Tables
Type 1
Type 2
16 50 mV
100 150 mV
V_IT−
Negative-going differential input voltage threshold See Function Tables
Type 1 −50 20
mV
Type 2 50 94
mV
V_OH
High-level output voltage (LVTTL output)
I_OH = −8mA
V_OL
Low-level output voltage (LVTTL output)
I_OL = 8mA
I_OZ
TRI-STATE output current
V_O = 0V or 3.6V
I_OSR
Short-circuit receiver output current (LVTTL output) V_O = 0V
2.4 2.7
V
0.28 0.4
V
−10
10
μA
-50 -90 mA
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