DS91M040 Datasheet, PDF (12/16 Pages) National Semiconductor (TI) – 125 MHz Quad M-LVDS Transceiver

Truth Tables
DS91M040 Transmitting
Inputs
RE DE
DI
X
H
H
X
H
L
X
L
X
Outputs
B
A
L
H
H
L
Z
Z
X — Don't care condition
Z — High impedance state
DS91M040 as Type 1 Receiving
Inputs
Output
FSEN RE DE
A−B
RO
L
L
L
≥ +0.05V
H
L
L
L
≤ −0.05V
L
L
L
L
0V
X
L
H
L
X
Z
X — Don't care condition
Z — High impedance state
DS91M040 as Type 2 Receiving
Inputs
Output
FSEN RE DE
A−B
R
H
L
L
≥ +0.15V
H
H
L
L
≤ +0.05V
L
H
L
L
0V
L
H
H
L
X
Z
X — Don't care condition
Z — High impedance state
DS91M040 Type 1 Receiver Input Threshold Test Voltages
Applied Voltages
V_IA
2.400V
0.000V
3.800V
3.750V
−1.350V
−1.400V
V_IB
0.000V
2.400V
3.750V
3.800V
−1.400V
−1.350V
Resulting Differential Input
Voltage
V_ID
2.400V
−2.400V
0.050V
−0.050V
0.050V
−0.050V
Resulting Common-Mode
Input Voltage
V_ICM
1.200V
1.200V
3.775V
3.775V
−1.375V
−1.375V
H — High Level
L — Low Level
Output state assumes that the receiver is enabled (RE = L)
Receiver
Output
R
H
L
H
L
H
L
DS91M040 Type 2 Receiver Input Threshold Test Voltages
Applied Voltages
V_IA
2.400V
0.000V
3.800V
3.800V
−1.250V
−1.350V
V_IB
0.000V
2.400V
3.650V
3.750V
−1.400V
−1.400V
Resulting Differential Input
Voltage
V_ID
2.400V
−2.400V
0.150V
0.050V
0.150V
0.050V
Resulting Common-Mode
Input Voltage
V_IC
1.200V
1.200V
3.725V
3.775V
−1.325V
−1.375V
H — High Level
L — Low Level
Output state assumes that the receiver is enabled (RE = L)
Receiver
Output
R
H
L
H
L
H
L
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