CD4541BC Datasheet, PDF (4/6 Pages) Fairchild Semiconductor – Programmable Timer

Truth Table
Pin
State
0
1
5
Auto Reset Operating Auto Reset Disabled
6
Timer Operational
Master Reset On
9
Output Initially Low
after Reset
Output Initially High
after Reset
10 Single Cycle Mode
Recycle Mode
Division Ratio Table
Number of
A
B
Counter Stages
n
0
0
13
0
1
10
1
0
8
1
1
16
Count
2ⁿ
8192
1024
256
65536
Operating Characteristics
With Auto Reset pin set to a ‘‘0’’ the counter circuit is initial-
ized by turning on power Or with power already on the
counter circuit is reset when the Master Reset pin is set to a
‘‘1’’ Both types of reset will result in synchronously reset-
ting all counter stages independent of counter state
The RC oscillator frequency is determined by the external
RC network i e
1
fe
if (1 kHz ^s f ^s 100 kHz)
2 3 R_tcC_tc
and R_S 2 R_tc where R_S ^t 10 kX
The time select inputs (A and B) provide a two-bit address
to output any one of four counter stages (2⁸ 2¹⁰ 2¹³ and
2¹⁶) The 2ⁿ counts as shown in the Division Ratio Table
represent the Q output of the Nth stage of the counter
When A is ‘‘1’’ 2¹⁶ is selected for both states of B
However when B is ‘‘0’’ normal counting is interrupted and
the 9th counter stage receives its clock directly from the
oscillator (i e effectively outputting 2⁸)
The Q Q select output control pin provides for a choice of
output level When the counter is in a reset condition and
Q Q select pin is set to a ‘‘0’’ the Q output is a ‘‘0’’ Corre-
spondingly when Q Q select pin is set to a ‘‘1’’ the Q output
is a ‘‘1’’
When the mode control pin is set to a ‘‘1’’ the selected
count is continually transmitted to the output But with
mode pin ‘‘0’’ and after a reset condition the RS flip-flop
resets (see Logic Diagram) counting commences and after
2^nb1 counts the RS flip-flop sets which causes the output
to change state Hence after another 2^nb1 counts the out-
put will not change Thus a Master Reset pulse must be
applied or a change in the mode pin level is required to
reset the single cycle operation
Power Dissipation Test
Circuit and Waveforms
Switching Time Test
Circuit and Waveforms
(R_tc and C_tc outputs are left open)
TL F 6001 – 3
TL F 6001 – 5
4
TL F 6001 – 4
TL F 6001 – 6