CD4027BM Datasheet, PDF (4/6 Pages) National Semiconductor (TI) – Dual J-K Master/Slave Flip-Flop with Set and Reset

AC Electrical Characteristics T_A e 25 C C_L e 50 pF t_rCL e t_fCL e 20 ns unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t_PHL or t_PLH
Propagation Delay Time
from Clock to Q or Q
V_DD e 5V
V_DD e 10V
V_DD e 15V
200
400
ns
80
160
ns
65
130
ns
t_PHL or t_PLH
Propagation Delay Time
from Set to Q or Reset to Q
V_DD e 5V
V_DD e 10V
V_DD e 15V
170
340
ns
70
140
ns
55
110
ns
t_PHL or t_PLH
Propagation Delay Time
from Set to Q or
Reset to Q
V_DD e 5V
V_DD e 10V
V_DD e 15V
110
220
ns
50
100
ns
40
80
ns
t_S
Minimum Data Setup Time
V_DD e 5V
V_DD e 10V
V_DD e 15V
135
270
ns
55
110
ns
45
90
ns
t_THL or t_TLH
Transition Time
V_DD e 5V
V_DD e 10V
V_DD e 15V
100
200
ns
50
100
ns
40
80
ns
f_CL
Maximum Clock Frequency
V_DD e 5V
25
5
(Toggle Mode)
V_DD e 10V
62
12 5
V_DD e 15V
76
15 5
MHz
MHz
MHz
t_rCL or t_fCL
Maximum Clock Rise
V_DD e 5V
15
ms
and Fall Time
V_DD e 10V
10
ms
V_DD e 15V
5
ms
t_W
Minimum Clock Pulse
V_DD e 5V
Width (t_WH e t_WL)
V_DD e 10V
V_DD e 15V
100
200
ns
40
80
ns
32
65
ns
t_WH
Minimum Set and
Reset Pulse Width
V_DD e 5V
V_DD e 10V
V_DD e 15V
80
160
ns
30
60
ns
25
50
ns
C_IN
Average Input Capacitance
Any Input
5
75
pF
C_PD
Power Dissipation Capacity
Per Flip-Flop
(Note 4)
35
pF
AC Parameters are guaranteed by DC correlated testing
Note 1 ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed They are not meant to imply that the
devices should be operated at these limits The table of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provides conditions for actual
device operation
Note 2 V_SS e 0V unless otherwise specified
Note 3 I_OH and I_OL are tested one output at a time
Note 4 C_PD determines the no load AC power consumption of any CMOS device For complete explanation see 54C 74C Family Characteristics application
note AN-90
4