CD4027BM Datasheet, PDF (1/6 Pages) National Semiconductor (TI) – Dual J-K Master/Slave Flip-Flop with Set and Reset

February 1988
CD4027BM CD4027BC Dual J-K Master Slave
Flip-Flop with Set and Reset
General Description
These dual J-K flip-flops are monolithic complementary
MOS (CMOS) integrated circuits constructed with N- and P-
channel enhancement mode transistors Each flip-flop has
independent J K set reset and clock inputs and buffered
Q and Q outputs These flip-flops are edge sensitive to the
clock input and change state on the positive-going transition
of the clock pulses Set or reset is independent of the clock
and is accomplished by a high level on the respective input
All inputs are protected against damage due to static dis-
charge by diode clamps to V_DD and V_SS
Features
Y _{Wide supply voltage range}
Y _{High noise immunity}
Y _{Low power TTL}
compatibility
Y _{Low power}
Y _{Medium speed operation}
3 0V to 15V
0 45 V_DD (typ )
Fan out of 2 driving 74L
or 1 driving 74LS
50 nW (typ )
12 MHz (typ )
with 10V supply
Schematic and Connection Diagrams
Dual-In-Line Package
TL F 5958 – 1
Order Number CD4027B
Top View
C1995 National Semiconductor Corporation TL F 5958
TL F 5958 – 2
RRD-B30M105 Printed in U S A