ADC10D1000QML Datasheet, PDF (39/64 Pages) National Semiconductor (TI) – Low Power, 10-Bit, Dual 1.0 GSPS or Single 2.0 GSPS A/DConverter

phase relationship and for the Q-channel: DQ- and DQd-to-
DCLKQ phase relationship.
To use this feature in ECM, use the DPS bit in the Configu-
ration Register (Addr: 0h; Bit: 14). See Configuration Register
1 for more information.
17.3.1.3 Calibration Pin (CAL)
The Calibration (CAL) Pin must be used to initiate an on-
command calibration event. The effect of calibration is to
maximize the dynamic performance. To initiate an on-com-
mand calibration via the CAL pin, bring the CAL pin high for
a minimum of t_{CAL_H} input clock cycles after it has been low
for a minimum of t_{CAL_L} input clock cycles. The CAL pin should
be held high when not in use to help insure no undesired cal-
ibrating in space environment. In ECM mode this pin remains
active and is Logically OR'd with the CAL bit.
To use this feature in ECM, use the CAL bit in the Configu-
ration Register (Addr: 0h; Bit: 15). See Section 17.4.3 Cali-
bration Feature for more information.
17.3.1.4 Power Down I-channel Pin (PDI)
The Power Down I-channel (PDI) Pin selects whether the I-
channel is powered down (logic-high) or active (logic-low).
The digital data output pins (both positive and negative) are
put into a high impedance state when the I-channel is pow-
ered down. Upon return to the active state, the pipeline will
contain meaningless information and must be flushed. The
supply currents (typicals and limits) are available for the I-
channel powered down or active and may be found in Table
11. It is recommended that the user thoroughly understand
how the PDI feature functions in relationship with the Cali-
bration feature and control them appropriately for his appli-
cation.
This pin remains active in ECM. In ECM, either this pin or the
PDI bit (Addr: 0h; Bit: 11) in the Control Register may be used
to power-down the I-channel. See Section 17.4.4 Power
Down Power Down for more information.
17.3.1.5 Power Down Q-channel Pin (PDQ)
The Power Down Q-channel (PDQ) Pin selects whether the
Q-channel is powered down (logic-high) or active (logic-low).
This pin functions similarly to the PDI pin, except that it applies
to the Q-channel. The PDI and PDQ pins function indepen-
dently of each other to control whether each I- or Q-channel
is powered down or active.
This pin remains active in ECM. In ECM, either this pin or the
PDQ bit (Addr: 0h; Bit: 10) in the Control Register may be
used to power-down the I-channe. See Section 17.4.4 Power
Down for more information.
17.3.1.6 Test Pattern Mode Pin (TPM)
The Test Pattern Mode (TPM) Pin selects whether the
output of the ADC10D1000 is a test pattern (logic-high) or the
converted input (logic-low). The ADC10D1000 can provide a
test pattern at the four output buses independently of the input
signal to aid in system debug. In TPM, the ADC is disengaged
and a test pattern generator is connected to the outputs, in-
cluding ORI and ORQ. See Section 17.4.2.6 Test Pattern
Mode for more information.
17.3.1.7 Full-Scale Input Range Pin (FSR)
The Full-Scale Input Range (FSR) Pin selects whether the
full-scale input range for both the I- and Q-channel is higher
(logic-high) or lower (logic-low). The input full-scale range is
specified as V_IN in Table 7. In Non-ECM, the full-scale input
range for each I- and Q-channel may not be set independent-
ly, but it is possible to do so in ECM. In ECM, the full-scale
input range may be set with 15-bits of precision; see FS_ADJ
in Table 7. The device must be calibrated following a change
in FSR to obtain optimal performance.
To use this feature in ECM, use the Configuration Register
(Addr: 3h and Bh). See Section 17.4.1 Input Control and Ad-
just for more information.
17.3.1.8 LVDS Output Common-mode Pin (V_BG)
The V_BG Pin serves a dual purpose and may either provide
the bandgap output voltage or select whether the LVDS out-
put common-mode voltage is higher (logic-high) or lower
(floating). The LVDS output common-mode voltage is speci-
fied as V_OS and may be found in Table 10. This pin is always
active, in both ECM and Non-ECM. See Section 17.4.2 Out-
put Control and Adjust for more information.
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