ADC10D1000QML Datasheet, PDF (1/64 Pages) National Semiconductor (TI) – Low Power, 10-Bit, Dual 1.0 GSPS or Single 2.0 GSPS A/DConverter

ADC10D1000QML
May 10, 2010
Low Power, 10-Bit, Dual 1.0 GSPS or Single 2.0 GSPS A/D
Converter
1.0 General Description
The ADC10D1000 is the latest advance in National's Ultra-
High-Speed ADC family of products. This low-power, high-
performance CMOS analog-to-digital converter digitizes sig-
nals at 10-bit resolution at sampling rates of up to 1.0 GSPS
in dual channel mode or 2.0 GSPS in single channel mode.
The ADC10D1000 achieves excellent accuracy and dynamic
performance while consuming a typical 2.9 Watts of power.
This space grade, Radiation Tolerant part is rad hard to a
single event latch up level of greater than 120MeV and a total
dose (TID) of 100 krad(Si). The product is packaged in a her-
matic 376 column thermally enhanced CCGA package rated
over the temperature range of -55°C to +125°C.
The ADC10D1000 builds upon the features, architecture and
functionality of the 8-bit GHz family of ADCs. New features
include an auto-sync feature for multi-chip synchronization,
independent programmable15-bit gain and 12-bit offset ad-
justment per channel, LC tank filter on the clock input, and the
option of two's complement format for the digital output data.
The unique folding and interpolating architecture, the fully dif-
ferential comparator design, the innovative design of the in-
ternal track-and-hold amplifier and the self-calibration
scheme enable a very flat response of all dynamic parameters
beyond Nyquist, producing a high 8.9 Effective Number of Bits
(ENOB) with a 498 MHz input signal and a 1.0 GHz sample
rate while providing a 10^−18 Code Error Rate (C.E.R.) Con-
suming a typical 2.9 Watts in Non-Demultiplex Mode at 1.0
GSPS from a single 1.9 Volt supply, this device is guaranteed
to have no missing codes over the full operating temperature
range.
Each channel has its own independent DDR Data Clock,
DCLKI and DCLKQ, which are in phase when both channels
are powered up, so that only one Data Clock could be used
to capture all data, which is sent out at the same rate as the
input sample clock. If the 1:2 Demultiplexed Mode is selected,
a second 10-bit LVDS bus becomes active for each channel,
such that the output data rate is sent out two times slower, but
two times wider to relax data-capture timing margin. The two
channels (I and Q) can also be interleaved (DES Mode) and
used as a single 2.0 GSPS ADC to sample on the Q input.
The output formatting is offset binary or two's complement
and the Low Voltage Differential Signaling (LVDS) digital out-
puts are compatible with IEEE 1596.3-1996, with the excep-
tion of an adjustable common mode voltage between 0.8V
and 1.2V.
2.0 Features
■ ^{Total Ionizing Dose}
■ ^{Single Event Latch-up}
100 krad(Si)
120 Mev-cm²/mg
■ ^{Excellent accuracy and dynamic performance}
■ ^{Low power consumption}
■ ^{R/W SPI Interface for Extended Control Mode}
■ ^{Internally terminated, buffered, differential analog inputs}
■ ^{Ability to interleave the two channels to operate one}
channel at twice the conversion rate
■ ^{Test patterns at output for system debug}
■ ^{Programmable 15-bit gain and 12-bit plus sign offset}
adjustments
■ ^{Option of 1:2 demuxed or 1:1 non-demuxed LVDS outputs}
■ ^{Auto-sync feature for multi-chip systems}
■ ^{Single 1.9V±0.1V power supply}
■ ^{376 Ceramic Column Grid Array package (28.2mm x}
28.2mm x 3.1mm with 1.27mm ball-pitch)
3.0 Key Specifications
(Non-Demux Non-DES Mode, Fs = 1.0 GSPS, Fin = 248 MHz)
■ ^Resolution
10 Bits
■ ^{Conversion Rate}
— Dual channels at 1.0 GSPS (typ)
— Single channel at 2.0 GSPS (typ)
■ ^{Code Error Rate}
■ ^ENOB
■ ^SNR
■ ^SFDR
■ ^{Full Power Bandwidth}
■ ^DNL
10 ^−18 (typ)
9.0 bits (typ)
56.1 dBc (typ)
63 dBc (typ)
2.8 GHz (typ)
±0.2 LSB (typ)
■ ^{Power Consumption}
— Single Channel Enabled
— Dual Channels Enabled
— Power Down Mode
1.64W (typ)
2.9W (typ)
6 mW (typ)
4.0 Applications
■ ^{Data Acquisition Systems}
■ ^{Wideband Communications}
■ ^{Direct RF Down Conversion}
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www.national.com