ADC08D1520QML Datasheet, PDF (37/46 Pages) National Semiconductor (TI) – Low Power, 8-Bit, Dual 1.5 GSPS or Single 3.0 GSPS A/D Converter

1.5 MULTIPLE ADC SYNCHRONIZATION
The ADC08D1520QML has the capability to precisely reset
its sampling clock input to DCLK output relationship as de-
termined by the user-supplied DCLK_RST pulse. This allows
multiple ADCs in a system to have their DCLK (and data) out-
puts transition at the same time with respect to the shared
CLK input that they all the ADCs use for sampling.
The DCLK_RST signal must observe some timing require-
ments that are shown in Figure 7, Figure 8 and Figure 9 of the
Timing Diagrams. The DCLK_RST pulse must be of a mini-
mum width and its deassertion edge must observe setup and
hold times with respect to the CLK input rising edge. These
timing specifications are listed as t_RH, t_RS, and t_RPW in the
Converter Electrical Characteristics.
The DCLK_RST signal can be asserted asynchronous to the
input clock. If DCLK_RST is asserted, the DCLK output is held
in a designated state. The state in which DCLK is held during
the reset period is determined by the mode of operation (SDR/
DDR) and the setting of the Output Edge configuration pin or
bit. (Refer to Figure 7, Figure 8 and Figure 9 for the DCLK
reset state conditions). Therefore, depending upon when the
DCLK_RST signal is asserted, there may be a narrow pulse
on the DCLK line during this reset event. When the
DCLK_RST signal is de-asserted in synchronization with the
CLK rising edge, the 4th or 5th CLK falling edge synchronizes
the DCLK output with those of other ADC08D1520QMLs in
the system. The DCLK output is enabled again after a con-
stant delay (relative to the input clock frequency) which is
equal to the CLK input to DCLK output delay (t_SD). The device
always exhibits this delay characteristic in normal operation.
As shown in Figure 7, Figure 8 and Figure 9of the Timing Di-
agrams, there is a delay from the deassertion of DCLK_RST
to the reappearance of DCLK, which is equal to several CLK
cycles of delay plus t_SD. Note that the deassertion of
DCLK_RST is not latched in until the next falling edge of CLK.
For 1:2 Demux DDR 0 deg Mode, there are five CLK cycles
of delay; for all other modes, there are four CLK cycles of
delay.
If the device is not programmed to allow DCLK to run contin-
uously, DCLK will become inactive during a calibration cycle.
Therefore, it is strongly recommended that DCLK only be
used as a data capture clock and not as a system clock.
The DCLK_RST pin should NOT be brought high while the
calibration process is running (while CalRun is high). Doing
so could cause a digital glitch in the digital circuitry, resulting
in corruption and invalidation of the calibration. (See Applica-
tion Information Section 2.4.3)
1.6 ADC TEST PATTERN
To aid in system debug, the ADC08D1520QML has the ca-
pability of providing a test pattern at the four output ports
completely independent of the input signal. The ADC is dis-
engaged and a test pattern generator is connected to the
outputs including OR. The test pattern output is the same in
DES Mode and Non-DES Mode. Each port is given a unique
8-bit word, alternating between 1's and 0's as described in the
Table 6.
Time
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
TABLE 6. Test Pattern by Output Port
in 1:2 Demultiplex Mode
Qd Id
Q
I OR Comments
01h 02h 03h 04h 0
FEh FDh FCh FBh 1
01h 02h 03h 04h 0
FEh FDh FCh FBh 1
Pattern
Sequence
n
01h 02h 03h 04h 0
01h 02h 03h 04h 0
FEh FDh FCh FBh 1
01h 02h 03h 04h 0
FEh FDh FCh FBh 1
Pattern
Sequence
n+1
01h 02h 03h 04h 0
01h 02h 03h 04h 0
Pattern
...
...
... ... ... Sequence n+2
With the part programmed into the Non-Demultiplex Mode,
the test pattern’s order will be as described in Table 7.
TABLE 7. Test Pattern by Output Port in
Non-Demultiplex Mode
Time
Q
I
OR Comments
T0
01h
02h
0
T1
FEh
FDh
1
T2
01h
02h
0
T3
01h
02h
0
T4
FEh
FDh
1
Pattern
Sequence
T5
FEh
FDh
1
n
T6
01h
02h
0
T7
01h
02h
0
T8
FEh
FDh
1
T9
01h
02h
0
T10
01h
02h
0
T11
FEh
FDh
1
T12
01h
02h
0
Pattern
Sequence
T13
01h
02h
0
n+1
T14
FEh
FDh
1
T15
...
...
...
To ensure that the test pattern starts synchronously in each
port, set DCLK_RST while writing the Test Pattern Output bit
in the Extended Configuration Register. The pattern appears
at the data output ports when DCLK_RST is cleared low. The
test pattern will work at speed and will work with the device in
the SDR, DDR and the Non-Demultiplex output modes.
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