DP8520A Datasheet, PDF (36/70 Pages) National Semiconductor (TI) – DP8520A/DP8521A/DP8522A microCMOS Programmable 256k/1M/4M Video RAM Controller/Drivers

8 0 RAS and CAS Configuration Modes (Continued)
8 5 PAGE BURST MODE
In a static column page or burst mode system the least
significant bits must be tied to the column address in order
to ensure that the page burst accesses are to sequential
memory addresses as shown in Figure 44 In a nibble mode
system the two least significant address bits (A2 A3) must
be tied to the highest row and column address inputs (de-
pends on VRAM size) to ensure that the toggling bits of
nibble mode VRAMs are to sequential memory addresses
The ECAS inputs may then be toggled with the DP8520A
21A 22A’s address latches in fall-through mode while
AREQ is asserted The ECAS inputs can also be used to
select individual bytes When using nibble mode VRAMS
the third and fourth address bits can be tied to the bank
select inputs to perform memory interleaving In page or
static column modes the two address bits after the page
size can be tied to the bank select inputs to select a new
bank if the page size is exceeded
TL F 9338 – 95
See table below for row column bank address bit map A0 A1 are used for byte addressing in this example
Addresses Nibble Mode
Page Mode Static Column Mode Page Size
256 Bits Page 512 Bits Page 1024 Bits Page 2048 Bits Page
Column
Address
R9 C9 e A2 A3 C0 – 7 e A2 – 9 C0 – 8 e A2 – 10 C0 – 9 e A2 – 11
C0 – 10 e A2 – 12
C0 – 8 e X
C8 – 10 e X
C9 10 e X
C10 e X
Row
X
X
X
X
X
Address
B0
A4
A10
A11
A12
A13
B1
A5
A11
A12
A13
A14
Assuming 1 M-bit Vrams are being used
Assume that the least significant address bits are used for byte addressing Given a 32-bit system A0 A1 would be
used for byte addressing
X e DON’T CARE the user can do as he pleases
FIGURE 44 Page Static Column Nibble Mode System
36