DP8520A Datasheet, PDF (1/70 Pages) National Semiconductor (TI) – DP8520A/DP8521A/DP8522A microCMOS Programmable 256k/1M/4M Video RAM Controller/Drivers

PRELIMINARY
May 1992
DP8520A DP8521A DP8522A microCMOS Programmable
256k 1M 4M Video RAM Controller Drivers
General Description
The DP8520A 21A 22A video RAM controllers provide a
low cost single chip interface between video RAM and all
8- 16- and 32-bit systems The DP8520A 21A 22A gener-
ate all the required access control signal timing for VRAMs
An on-chip refresh request clock is used to automatically
refresh the VRAM array Refreshes and accesses are arbi-
trated on chip If necessary a WAIT or DTACK output in-
serts wait states into system access cycles including burst
mode accesses RAS low time during refreshes and RAS
precharge time after refreshes and back to back accesses
are guaranteed through the insertion of wait states Sepa-
rate on-chip precharge counters for each RAS output can
be used for memory interleaving to avoid delayed back to
back accesses because of precharge An additional feature
of the DP8522A is two access ports to simplify dual access-
ing Arbitration among these ports and refresh is done on
chip
Features
Y _{On chip high precision delay line to guarantee critical}
VRAM access timing parameters
Y _{microCMOS process for low power}
Y _{High capacitance drivers for RAS CAS DT OE and}
VRAM address on chip
Y _{On chip support for nibble page and static column}
VRAMs
Y _{Byte enable signals on chip allow byte writing in a word}
size up to 16 bits with no external logic
Y _{Selection of controller speeds 20 MHz and 25 MHz}
Y _{On board Port A Port B (DP8522A only) refresh arbitra-}
tion logic
Y _{Direct interface to all major microprocessors (applica-}
tion notes available)
Y _{4 RAS and 4 CAS drivers (the RAS and CAS configura-}
tion is programmable)
Control
DP8520A
DP8521A
DP8522A
of Pins
(PLCC)
68
68
84
of Address
Outputs
9
10
11
Largest
VRAM
Possible
256 kbit
1 Mbit
4 Mbit
Direct Drive
Memory
Capacity
4 Mbytes
16 Mbytes
64 Mbytes
Access
Ports
Available
Single Access Port
Single Access Port
Dual Access Ports (A and B)
Block Diagram
DP8520A 21A 22A VRAM Controller
FIGURE 1
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