OPA4830 Datasheet, PDF (35/45 Pages) National Semiconductor (TI) – Quad, Low-Power, Single-Supply, Wideband Operational Amplifier

OPA4830
www.ti.com.................................................................................................................................................... SBOS350A – DECEMBER 2006 – REVISED MAY 2008
DC ACCURACY AND OFFSET CONTROL
The balanced input stage of a wideband
voltage-feedback op amp allows good output dc
accuracy in a wide variety of applications. The
power-supply current trim for the OPA4830 gives
even tighter control than comparable products.
Although the high-speed input stage does require
relatively high input bias current (typically 5µA out of
each input terminal), the close matching between
them may be used to reduce the output dc error
caused by this current. This reduction is achieved by
matching the dc source resistances appearing at the
two inputs. Evaluating the configuration of Figure 74
(which has matched dc input resistances), using
worst-case +25°C input offset voltage and current
specifications, gives a worst-case output offset
voltage equal to Equation 10:
(NG = noninverting signal gain at dc)
±(NG ´ V_OS(MAX)) + (R_F ´ I_OS(MAX))
= ±(2 ´ 8mV) ´ (375W ´ 1.1mA)
= ±16.41mV
(10)
A fine-scale output offset null, or dc operating point
adjustment, is often required. Numerous techniques
are available for introducing dc offset control into an
op amp circuit. Most of these techniques are based
on adding a dc current through the feedback resistor.
In selecting an offset trim method, one key
consideration is the impact on the desired signal path
frequency response. If the signal path is intended to
be noninverting, the offset control is best applied as
an inverting summing signal to avoid interaction with
the signal source. If the signal path is intended to be
inverting, applying the offset control to the
noninverting input may be considered. Bring the dc
offsetting current into the inverting input node through
resistor values that are much larger than the signal
path resistors. This configuration ensures that the
adjustment circuit has minimal effect on the loop gain
and therefore the frequency response.
THERMAL ANALYSIS
Maximum desired junction temperature sets the
maximum allowed internal power dissipation, as
described below. In no case should the maximum
junction temperature be allowed to exceed +150°C.
Operating junction temperature (T_J) is given by T_A +
P_D × θ_JA. The total internal power dissipation (P_D) is
the sum of quiescent power (P_DQ) and additional
power dissipated in the output stage (P_DL) to deliver
load power. Quiescent power is simply the specified
no-load supply current times the total supply voltage
across the part. P_DL depends on the required output
signal and load; though, for resistive loads connected
to mid-supply (V_S/2), P_DL is at a maximum when the
output is fixed at a voltage equal to V_S/4 or 3V_S/4.
Under this condition, P_DL = V_S2/(16 × R_L), where R_L
includes feedback network loading.
Note that it is the power in the output stage, and not
into the load, that determines internal power
dissipation.
As a worst-case example, compute the maximum T_J
using an OPA4830 (TSSOP-14 package) in the circuit
of Figure 72 operating at the maximum specified
ambient temperature of +85°C and driving a 150Ω
load at mid-supply.
P_D = 5V ´ 19mA + 4 ´ 5²/(4 ´ (150W || 750W)) = 295mW
Maximum T_J = +85°C + (0.295W ´ 95°C/W) = +113°C
Although this value is still well below the specified
maximum junction temperature, system reliability
considerations may require lower ensured junction
temperatures. The highest possible internal
dissipation occurs if the load requires current to be
forced into the output at high output voltages or
sourced from the output at low output voltages. This
puts a high current through a large internal voltage
drop in the output transistors.
Copyright © 2006–2008, Texas Instruments Incorporated
Product Folder Link(s): OPA4830
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