DP83850C Datasheet, PDF (31/37 Pages) National Semiconductor (TI) – 100 Mb/s TX/T4 Repeater Interface Controller (100RIC™)

6.0 A.C. and D.C. Specifications (Continued)
6.2.4 Inter Repeater Collision Timing
Description
T19 _{IR_VECT[4:0] change to /IR_COL_OUT assertion[de-assertion]}⁹
T20 /IR_COL_OUT assertion to IRD_ODIR de-assertion
T20A _{/ACTIVEO low to IR_VECT[4:0] feedback}^10,11
Min Max Units
17 ns
15 ns
20 ns
Note 9: This timing refers to the condition where the repeater has detected a change from its driven arbitration vector to
what is seen on the IR_VECT[4:0] bus. In other words, an “Inter Repeater” collision is occurring.
Note 10: This timing refers to the condition where the DP83850C first drives its vector onto IR_VECT[4:0] at the begin-
ning of a packet. The IR_VECT[4:0] feedback (possibly returning from an external bus) must be stable by this time.
Note 11: Guaranteed By Design.
6.2.5 Management Bus - Output Mode Timing
Description
T21 /M_DV assertion [de-assertion] from M_CK high
T22 MD[3:0] or /M_ER valid from M_CK high
T23 Removed
31
Min Max
4
15
4
15
Units
ns
ns
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