DP83850C Datasheet, PDF (1/37 Pages) National Semiconductor (TI) – 100 Mb/s TX/T4 Repeater Interface Controller (100RIC™)

June 1998
DP83850C 100 Mb/s TX/T4 Repeater Interface Controller
(100RIC^™)
General Description
Features
The DP83850C 100 Mb/s TX/T4 Repeater Interface Con-
troller, known as 100RIC, is designed specifically to meet
the needs of today's high speed Ethernet networking sys-
tems. The DP83850C is fully compatible with the IEEE
802.3 repeater's clause 27.
The DP83850C supports up to twelve 100 Mb/s links with
its network interface ports. The 100RIC can be configured
to be used with either 100BASE-TX or 100BASE-T4 PHY
technologies. Larger repeaters with up to 372 ports may
be constructed by cascading DP83850Cs together using
the built-in Inter Repeater bus.
In conjunction with a DP83856 100 Mb/s Repeater Infor-
mation Base device, a DP83850C based repeater
becomes a managed entity that is compatible with IEEE
802.3u (clause 30), collecting and providing an easy inter-
face to all the required network statistics.
s IEEE 802.3u repeater and management compatible
s Supports Class II TX translational repeater and Class I
T4 repeater
s Supports 12 network connections (ports)
s Up to 31 repeater chips cascadable for larger hub appli-
cations (up to 372 ports)
s Separate jabber and partition state machines for each
port
s Management interface to DP83856 allows all repeater
MIBs to be maintained
s Large per-port management counters - reduces man-
agement CPU overhead
s On-chip elasticity buffer for PHY signal re-timing to the
DP83850C clock source
s Serial register interface - reduces cost
s Physical layer device control/status access available via
the serial register interface
s Detects repeater identification errors
s 132 pin PQFP package
System Diagram
DP83850C
100 Mb/s
Repeater Interface Controller
(100RIC8)
DP83856
100 Mb/s
Repeater Information Base
(100RIB)
Inter Repeater Bus
Management Bus
RX Enable [11..0]
MII
DP83840A
100 PHY
#0
100Mb/s
Ethernet
Ports
DP83223
100BASE-X
Transceiver
Port 0
DP83840A
100 PHY
#1
DP83223
100BASE-X
Transceiver
Port 1
DP83840A
100 PHY
#2
DP83223
100BASE-X
Transceiver
Port 2
(IR_COL, IR_DV)
DP83840A
100 PHY
#11
DP83223
100BASE-X
Transceiver
Port 11
Statistics
SRAM
Management
CPU
Program
Memory
Management
I/O Devices
Note: The above system diagram depicts the repeater configured in 100BASE-TX mode.
FAST^® is a registered trademark of Fairchild Semiconductor Corporation.
TRI-STATE^® is a registered trademark of National Semiconductor Corporation.
100RIC^™ is a trademark of National Semiconductor Corporation.
© 1998 National Semiconductor Corporation
www.national.com