PC87109VBE Datasheet, PDF (30/56 Pages) National Semiconductor (TI) – PC87109VBE Advanced UART and Infrared Controller

DMA SWAP
LOGIC
RECEIVER
CHANNEL
DMA LOGIC
RX_DMA
TRANSMITTER
CHANNEL
DMA LOGIC
TX_DMA
CONFIGURATION
MODULE
DMA
ENABLE
LOGIC
DRQ
DACK
DMA
HANDSHAKE
SIGNALS
DMASWP
Figure 3-12. DMA Control Signals Routing
3.3.3 LCR/BSR - Link Control/Bank Select Registers
These registers are the same as in bank 0.
3.3.4 EXCR2 - Extended Control Register 2
This register is used to configure the transmitter and receiver FIFOs, and the baud generator prescaler.
Upon reset all bits are set to 0.
Bits
Function
Reset State
B7
LOCK
0
B6
B5
B4
B3
B2
res
PRESL1 PRESL0 RF_SIZ1 RF_SIZ0
0
0
0
0
0
Figure 3-13. Extended Control Register 2
B1
TF_SIZ1
0
B1-0
TF_SIZ [1-0] - TX_FIFO Levels Select.
These bits select the number of levels for the TX_FIFO.
They are effective only when the FIFOs are enabled.
Bits 1-0
00
01
1x
TX_FIFO Levels
16
32
Reserved
B3-2
B5-4
RF_SIZ [1-0] - RX_FIFO Levels Select.
These bits select the number of levels for the RX_FIFO.
They are effective only when the FIFOs are enabled.
Bits 3-2
00
01
1x
RX_FIFO Levels
16
32
Reserved
PRESL [1-0] - Prescaler Select.
The prescaler divides the 24 MHz input clock frequency to provide the clock for the baud generator.
Bits 5-4
00
01
10
11
Prescaler Value
13.0
1.625
Reserved
1.0
B6
Reserved.
Read/write 0.
B0
TF_SIZ0
0
30
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