PC87109VBE Datasheet, PDF (19/56 Pages) National Semiconductor (TI) – PC87109VBE Advanced UART and Infrared Controller

EIR bits
3210
0001
0110
0100
1100
0010
Priority
Level
N/A
Highest
Second
Second
Third
Interrupt
Type
None
Line Status
Receiver
High-Data-
Level Event
RX_FIFO
Time-out
Transmitter
Low-Data-Level
Event
Interrupt Source
None
Parity error, or
Framing error, or
Data overrun, or
Break event
Receiver holding register full, or RX_FIFO
level equal to or above threshold
At least 1 character in RX_FIFO, and no
character input to or read from the
RX_FIFO for 4 character times
Transmitter holding register or TX_FIFO
empty
Interrupt Reset Control
N/A
Reading the LSR Register
Reading the RXD port, or RX_FIFO
level drops below threshold
Reading the RXD port
Reading the EIR register if this
interrupt is currently the highest
priority pending interrupt, or writing
into the TXD port
Table 3-3. Non-Extended Mode Interrupt Priorities
Extended Mode
The EIR register does not return an encoded value like in the non-extended mode. Each bit represents an event flag and is set to
1 when the corresponding event occurred or is pending, regardless of the setting of the corresponding bit in the IER register. Bits
7 (timer interrupt) is cleared when this register is read. Bit 4 is cleared when this register is read if an 8237 type DMA controller is
used. All other bits are cleared when the corresponding interrupts are acknowledged.
Bits
Function
B7
TMR_EV
Reset State
0
B6
SFIF_EV
0
B5
TXEMP_EV
1
B4
DMA_EV
0
B3
B2
res
LS_EV/
TXHLT_EV
0
0
Figure 3-4. Event Identification Register, Extended Mode
B1
TXLDL_EV
1
B0
RXHDL_EV
0
B0
RXHDL_EV - Receiver High-Data-Level Event.
FIFOs Disabled:
Set to 1 when one character is in the receiver holding register.
FIFOs Enabled:
Set to 1 when the RX_FIFO level is equal to or above the threshold level, or an RX_FIFO time-out has occurred.
B1
TXLDL_EV - Transmitter Low-Data-Level Event.
FIFOs Disabled:
Set to 1 when the transmitter holding register is empty.
FIFOs Enabled:
Set to 1 when the TX_FIFO level is below the threshold level.
B2 UART, Sharp-IR, SIR Modes
LS_EV - Link Status Event.
Set to 1 when a receiver error or break condition is reported.
Note that, when the FIFOs are enabled, the PE, FE and BRK conditions are only reported when the associated
character reaches the bottom of the RX_FIFO. An overrun error (OE) is reported as soon as it occurs.
MIR, FIR Modes
LS_EV/TXHLT_EV - Link Status/Transmitter Halted Event.
Set to 1 when any of the following conditions occurs:
1. EOF character reaches the bottom of the RX_FIFO
2. Receiver overrun
3. Transmitter under-run
4. Transmitter halted on frame end
CEIR Mode
LS_EV/TXHLT_EV - Link Status/Transmitter Halted.
Set to 1 when a receiver overrun or a transmitter under-run condition occurs.
19
www.national.com