LP3954 Datasheet, PDF (30/56 Pages) National Semiconductor (TI) – Advanced Lighting Management Unit

Logic Interface Characteristics
(1.65V ≤ V_DDIO ≤ V_DD1,2V) (Unless otherwise noted).
Symbol
Parameter
Conditions
Min
LOGIC INPUTS SS, SI, SCK/SCL, SYNC/PWM, IF_SEL, EN_FLASH
V_IL
Input Low Level
V_IH
Input High Level
I_I
Logic Input Current
I²C Mode
0.8×V_DDIO
−1.0
f_SCL
Clock Frequency
LOGIC OUTPUT SO
SPI Mode,
V_DDIO > 1.8V
SPI Mode,
1.65V ≤ V_DDIO < 1.8V
I_SO = 3 mA
V_OL
Output Low Level
V_DDIO > 1.8V
I_SO = 2 mA
1.65V ≤ V_DDIO < 1.8V
I_SO = −3 mA
V_OH
Output High Level
V_DDIO > 1.8V
I_SO = -2 mA
1.65V ≤ V_DDIO < 1.8V
I_L
Output Leakage Current V_SO = 2.8V
LOGIC OUTPUT SDA
V_DDIO − 0.5
V_DDIO − 0.5
V_OL
Output Low Level
I_SDA = 3 mA
Typ
Max
Units
0.2×V_DDIO
1.0
400
13
V
V
µA
kHz
MHz
5
MHz
0.3
0.5
V
0.3
0.5
V_DDIO − 0.3
V
V_DDIO − 0.3
1.0
µA
0.3
0.5
V
Control Interface
The LP3954 supports two different interface modes:
• SPI interface (4 wire, serial)
• I²C compatible interface (2 wire, serial)
User can define the serial interface by IF_SEL pin. IF_SEL=0
selects the I²C mode.
SPI INTERFACE
LP3954 is compatible with SPI serial bus specification and it operates as a slave. The transmission consists of 16-bit Write and
Read Cycles. One cycle consists of 7 Address bits, 1 Read/Write (RW) bit and 8 Data bits. RW bit high state defines a Write Cycle
and low defines a Read Cycle. SO output is normally in high-impedance state and it is active only when Data is sent out during a
Read Cycle. A pull-up resistor may be needed in SO line if a floating logic signal can cause unintended current consumption in the
input circuits where SO is connected.The Address and Data are transmitted MSB first. The Slave Select signal SS must be low
during the Cycle transmission. SS resets the interface when high and it has to be taken high between successive Cycles. Data is
clocked in on the rising edge of the SCK clock signal, while data is clocked out on the falling edge of SCK.
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SPI Write Cycle
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