LMC6061_14 Datasheet, PDF (3/21 Pages) National Semiconductor (TI) – PRECISION CMOS SINGLE MICROPOWER OPERATIONAL AMPLIFIER

LMC6061
www.ti.com
SNOS648D – NOVEMBER 1994 – REVISED MARCH 2013
DC Electrical Characteristics
Unless otherwise specified, all limits ensured for T_J = 25°C. Boldface limits apply at the temperature extremes. V⁺ = 5V, V^− =
0V, V_CM = 1.5V, V_O = 2.5V and R_L > 1M unless otherwise specified.
Symbol
Parameter
Conditions
Typ ⁽¹⁾
LMC6061AM
Limit ⁽²⁾
LMC6061AI LMC6061I
Limit ⁽²⁾
Limit ⁽²⁾
Units
V_OS
Input Offset Voltage
100
350
1200
350
800
μV
900
1300
Max
TCV_OS Input Offset Voltage
1.0
Average Drift
μV/°C
I_B
Input Bias Current
0.010
100
pA
4
4
Max
I_OS
Input Offset Current
0.005
100
pA
2
2
Max
R_IN
CMRR
+PSRR
Input Resistance
Common Mode Rejection
Ratio
0V ≤ V_CM ≤ 12.0V
V⁺ = 15V
Positive Power Supply
Rejection Ratio
5V ≤ V⁺ ≤ 15V
V_O = 2.5V
>10
85
75
70
85
75
70
Tera Ω
75
66
dB
72
63
Min
75
66
dB
72
63
Min
−PSRR
V_CM
Negative Power Supply
Rejection Ratio
Input Common-Mode
Voltage Range
0V ≤ V^− ≤ −10V
V⁺ = 5V and 15V
for CMRR ≥ 60 dB
100
−0.4
V⁺ − 1.9
A_V
Large Signal Voltage Gain R_L = 100 kΩ⁽³⁾ Sourcing
4000
84
70
−0.1
0
V⁺ − 2.3
V⁺ − 2.6
400
200
84
81
−0.1
0
V⁺ − 2.3
V⁺ − 2.5
400
300
74
71
−0.1
0
V⁺ − 2.3
V⁺ − 2.5
300
200
dB
Min
V
Max
V
Min
V/mV
Min
Sinking
3000
180
180
90
V/mV
70
R_L = 25 kΩ⁽³⁾ Sourcing
3000
400
150
100
60
Min
400
200
V/mV
150
80
Min
Sinking
2000
100
100
70
V/mV
35
50
35
Min
(1) For operating at elevated temperatures the device must be derated based on the thermal resistance θ_JA with P_D = (T_J–T_A)/θ_JA
(2) All limits are specified by testing or statistical analysis.
(3) V⁺ = 15V, V_CM = 7.5V and R_L connected to 7.5V. For Sourcing tests, 7.5V ≤ V_O ≤ 11.5V. For Sinking tests, 2.5V ≤ V_O ≤ 7.5V.
Copyright © 1994–2013, Texas Instruments Incorporated
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