LMC1982 Datasheet, PDF (3/14 Pages) National Semiconductor (TI) – Digitally-Controlled Stereo Tone and Volume Circuit with Two Selectable Stereo Inputs

Electrical Characteristics (Continued)
The following specifications apply for
0 dB, treble = 0 dB, enhanced stereo
V⁺ = 9V, f_IN = 1 kHz, input signal (300 mV) applied to INPUT
is off, and loudness is off unlessotherwise specified. All limits
1, volume =
apply for T_A
0
=
dB, bass =
T_J = +25˚C.
Symbol
Parameter
Conditions
Typical
Limit
Unit
(Note 6) (Note 7)
(Limit)
Channel-to-Channel Volume
All Volume Attenuation Settings
Tracking Error
from 0100010XXX101XXX (80 dB)
±0.1
±1.5
dB (min)
to 0100010XXX000000 (0 dB)
Mute Attenuation
Bass Gain Range
V_IN = 1.0 V_rms
f_IN = 100 Hz, Pins 13, 16
105
86
dB (max)
±12
±10.0
dB (min)
±14.0
dB (max)
Bass Tracking Error
Bass Step Size
f_IN = 100 Hz, Pins 13, 16
f_IN = 100 Hz, Pins 13, 16
(Relative to Previous Level)
±0.1
2.0
±1.5
1.5
2.5
dB (max)
dB (min)
dB (max)
Treble Gain Range
f_IN = 10 kHz, Pins 13, 16
±12
±10.0
dB (min)
±14.0
dB (max)
Treble Tracking Error
Treble Step Size
f_IN = 10 kHz, Pins 13, 16
f_IN = 10 kHz, Pins 13, 16
(Relative to Previous Level)
±0.1
2.0
±1.5
1.5
2.5
dB (max)
dB (min)
dB (max)
Enhanced Stereo Cross
Coupling
(Note 10)
−4.4
−2.5
dB (min)
−6.9
dB (max)
Frequency Response
V_IN Applied to Input 1 and Input 2;
f_IN = 20 Hz − 20 kHz
(Relative to Signal Amplitude at 1 kHz)
±0.1
±1.0
dB (max)
Loudness
Volume Attenuator = 40 dB, Loudness
on (See Figure 5)
Gain at 100 Hz (Referenced
11.5
13.5
dB (max)
to Gain at 1 kHz)
9.5
dB (min)
Gain at 10 kHz (Referenced
6.5
8.5
dB (max)
to Gain at 1 kHz)
4.5
dB (min)
Signal-to-Noise Ratio
Channel Balance
V_IN = 1.0 V_rms, A Weighted,
Measured at 1 kHz, R_S = 470Ω
All Volume Settings
95
90
dB (min)
0.2
1.0
dB (max)
Channel Separation
Input Pins 4, 25: Output Pins 13, 16;
80
60
dB (min)
Input-Input Isolation
PSSR Power Supply Rejection Ratio
V_IN = 1.0V_rms (Note 8)
470Ω to AC Ground on Unused Input
V⁺ = 9 V_DC; 200 mV_rms, 100 Hz
Sinewave Applied to Pin 26
95
60
dB (min)
32
28
dB (min)
f_CLK
Clock Frequency
5.0
1.0
MHz
(max)
V_IN(1) Logic “1” Input Voltage
Pins 1, 27, 28 (IM Bus)
Pins 2, 3
1.3
2.0
V (min)
2.9
5.5
V (min)
V_IN(0) Logic “0” Input Voltage
Pins 1, 27, 28 (IM Bus)
Pins 2, 3
0.4
0.8
V (max)
1.2
3.5
V (max)
V_OUT(1) Logic “1” Output Voltage
V_OUT(0) Logic “0” Output Voltage
Pin 28 (IM Bus)
Pin 28 (IM Bus)
2.0
V (min)
0.4
0.8
V (max)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the deivce may occur. Operating Ratings indicate conditions for which the device is func-
tional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed speci-
fications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are specified with respect to ground.
Note 3: When the input voltage (V_IN) at any pin exceeds the power supply voltages (V_IN < V^− or V_IN > V⁺) the absolute value of the current at that pin should be
limited to 5 mA or less. The 20 mA package input current limits the number of pins that can exceed the power supply voltages with 5 mA current limit to four.
3
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