LMC1982 Datasheet, PDF (11/14 Pages) National Semiconductor (TI) – Digitally-Controlled Stereo Tone and Volume Circuit with Two Selectable Stereo Inputs

Application Information (Continued)
As shown in Table 1, loudness and enhanced stereo are
controlled through the same address. It is important to re-
member to set both functions to the correct value any time
either of these functions is updated.
DS011028-9
FIGURE 5. Loudness Control Circuit
ENHANCED STEREO
The LMC1982 has an enhanced stereo effect that can be
achieved by cross-coupling reverse phase information be-
tween the left and right stereo channels. This feature can
help improve the apparent stereo channel separation when,
because of cabinet or equipment limitations, the left and right
speakers are closer to each other than optimum.
Enhanced stereo is created by connecting an external fre-
quency shaping RC network between the OUTPUT opera-
tional amplifiers’ inverting inputs through an internal CMOS
switch (see Figure 6). The external network couples 60% of
each channel’s output to the opposite channel’s inverting in-
put. This cancels a portion of the signal common to both
channels.
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FIGURE 6. Enhanced Stereo Circuit
The desired 60% cross-coupling is accomplished through
the internal 6.5 kΩ feedback resistor and an external 10 kΩ
resistor. Bass frequency cancellation is prevented by using a
0.047 µF coupling capacitor to couple only frequencies
above 330 Hz. Switching noise is eliminated by using a
680 kΩ resistor across the 0.047 µF. R3, R4 and C6 can be
eliminated if enhanced stereo is not desired.
As shown in Table 1, enhanced stereo and loudness are
controlled through the same address. It is important to re-
member to set both functions to the correct value any time
either of these functions is updated.
SERIAL DATA COMMUNICATION
The LMC1982 uses the INTERMETAL serial bus (IM Bus)
standard. Serial data information is sent to the LMC1982
over a three wire IM Bus consisting of Clock (CLK), Data
(DATA), and Identity (ID). The DATA line is bidirectional and
the CLK and ID lines are unidirectional from the micropro-
cessor or micontroller to the LMC1982. The LMC1982’s bidi-
rectional capability is accomplished by using an open drain
output on the DATA line and an external 1 kΩ pull-up resistor.
The LMC1982 responds to address values from 01000000
(40_H) through 01000111 (47_H). The addresses select one of
the eight available functions (see Table 1). The IM Bus’ lines
have a logic high standby state when using TTL logic levels.
As shown in Figure 7, data transmission is initiated by low
levels on CLK and ID. Next, eight address bits are sent. This
address information includes the code to select one of the
LMC1982’s desired functions. Each address bit is clocked in
on the rising edge of CLK. The ID line is taken high after the
eight bits of address data are received by the LMC1982. The
controlling system continues toggling the CLK line eight
more times. Data that determines the selected function’s op-
erating point is written into, or single bit information on DIGI-
TAL INPUT 1 or DIGITAL INPUT 2 is read from, the
LMC1982. Finally, the end of transmission is signalled by
pulsing the ID line low for a minimum of 1 µs. The transmit-
ted function data is latched and the function changes to its
new setting.
Table 1 also details the serial data structure, range, and bit
assignments that sets each function’s operating point. The
volume and tone controls’ function control data binarily incre-
ments from zero to maximum as the function’s operating
point changes from 80 dB attenuation to 0 dB attenuation
(volume) or −12 dB to +12 dB (tone controls). Note that not
all data bits are needed by each function. The extra bits
shown as “X”s (“don’t cares”) are position holders and have
no affect on a respective function. They are necessary to
properly position the data in the LMC1982’s internal data
shift register. Unexpected results may take place if these bits
are not sent.
The LMC1982’s internal data shift register can handle either
a 16-bit word or two 8-bit serial data transmissions. It is the
final 8 bits of data received before the ID line goes high that
are used as the LMC1982 selection and function addresses.
The final eight bits after the ID line returns high are used to
change a function’s operating point. CLK must be stopped
when the final 8 data bits are received. The data stored in the
internal data latch remains unchanged until the ID is pulsed,
signifying the end of data transmission. When ID is pulsed,
the new data in the data shift register is latched into the data
latch and the selected function takes on a new operating
point.
A complete description and more information concerning the
IM Bus is given in the appendix of ITT’s CCU2000
datasheet.
DIGITAL I/O
The LMC1982’s two Digital Input pins, 2 and 3, provide
single-bit communication between a peripheral device and
the controller over the IM Bus. Each pin has an internal
30 kΩ pull-up resistor. Therefore, these pins should be con-
nected to open collector/drain outputs. The type of informa-
tion that could be received on these lines and retrieved by a
controller include FM stereo pilot indication, power on/off,
Secondary Audio Program (SAP), etc.
According to Table 1, the logic state of DIGITAL INPUT 1 and
DIGITAL INPUT 2 is latched and can be retrieved over the IM
Bus using the read command (47_H). The single-bit informa-
tion sent on the IM Bus is active low since these lines are in-
ternally pulled high.
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