DS90LV028A_05 Datasheet, PDF (3/10 Pages) National Semiconductor (TI) – 3V LVDS Dual CMOS Differential Line Receiver

Note 7: Generator waveform for all tests unless otherwise specified: f = 1 MHz, Z_O = 50Ω, t_r and t_f (0% to 100%) ≤ 3 ns for R_IN.
Note 8: t_SKD1 is the magnitude difference in differential propagation delay time between the positive-going-edge and the negative-going-edge of the same channel.
Note 9: t_SKD2 is the differential channel-to-channel skew of any event on the same device. This specification applies to devices having multiple receivers within the
integrated circuit.
Note 10: t_SKD3, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices at the same V_CC
and within 5˚C of each other within the operating temperature range.
Note 11: t_SKD4, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over the
recommended operating temperature and voltage ranges, and across process distribution. t_SKD4 is defined as |Max − Min| differential propagation delay.
Note 12: V_CC is always higher than R_IN+ and R_IN− voltage. R_IN+ and R_IN− are allowed to have voltage range −0.05V to +3.05V. V_ID is not allowed to be greater
than 100 mV when V_CM = 0V or 3V.
Note 13: f_MAX generator input conditions: t_r = t_f < 1 ns (0% to 100%), 50% duty cycle, differential (1.05V to 1.35 peak to peak). Output criteria: 60%/40% duty cycle,
V_OL (max 0.4V), V_OH (min 2.7V), load = 15 pF (stray plus probes).
Parameter Measurement Information
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FIGURE 1. Receiver Propagation Delay and Transition Time Test Circuit
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FIGURE 2. Receiver Propagation Delay and Transition Time Waveforms
Typical Application
Balanced System
FIGURE 3. Point-to-Point Application
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Applications Information
General application guidelines and hints for LVDS drivers
and receivers may be found in the following application
notes: LVDS Owner’s Manual (lit #550062-002), AN-808,
AN-977, AN-971, AN-916, AN-805, AN-903.
LVDS drivers and receivers are intended to be primarily used
in an uncomplicated point-to-point configuration as is shown
in Figure 3. This configuration provides a clean signaling
environment for the fast edge rates of the drivers. The re-
ceiver is connected to the driver through a balanced media
which may be a standard twisted pair cable, a parallel pair
cable, or simply PCB traces. Typically the characteristic
impedance of the media is in the range of 100Ω. A termina-
tion resistor of 100Ω should be selected to match the media,
and is located as close to the receiver input pins as possible.
The termination resistor converts the driver output (current
mode) into a voltage that is detected by the receiver. Other
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