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DS90LV011AH Datasheet, PDF (3/5 Pages) National Semiconductor (TI) – HIGH TEMPERATURE 3V LVDS DIFFERENTIAL DRIVER
Switching Characteristics (Continued)
Note 4: Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.
Note 5: These parameters are guaranteed by design. The limits are based on statistical analysis of the device performance over PVT (process, voltage,
temperature) ranges.
Note 6: CL includes probe and fixture capacitance.
Note 7: Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50Ω, tr ≤ 1 ns, tf ≤ 1 ns (10%-90%).
Note 8: The DS90LV011AH is a current mode device and only function with datasheet specification when a resistive load is applied to the drivers outputs.
Note 9: tSKD1, |tPHLD − tPLHD|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of
the same channel.
Note 10: tSKD3, Differential Part to Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This
specification applies to devices at the same VDD and within 5˚C of each other within the operating temperature range.
Note 11: tSKD4, part to part skew, is the differential channel to channel skew of any event between devices. This specification applies to devices over recommended
operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max − Min| differential propagation delay.
Note 12: fMAX generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, 0V to 3V. Output criteria: duty cycle = 45%/55%, VOD > 250mV. The
parameter is guaranteed by design. The limit is based on the statistical analysis of the device over the PVT range by the transitions times (tTLH and tTHL).
Parameter Measurement Information
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FIGURE 1. Differential Driver DC Test Circuit
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FIGURE 2. Differential Driver Full Load DC Test Circuit
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FIGURE 3. Differential Driver Propagation Delay and Transition Time Test Circuit
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