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DS90CP22_07 Datasheet, PDF (3/10 Pages) National Semiconductor (TI) – 800 Mbps 2x2 LVDS Crosspoint Switch | |||
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AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified (Note 4)
Symbol
Parameter
Conditions
Min Typ Max Units
TSET
Input to SEL Setup Time, Figures 1, 2
(Note 5)
0.7 0.5
ns
THOLD
Input to SEL Hold Time, Figures 1, 2
(Note 5)
1.0 0.5
ns
TSWITCH SEL to Switched Output, Figures 1, 2
0.9
1.2
1.7
ns
TPHZ
Disable Time (Active to TRI-STATE) High to Z, Figure 3
2.1
4.0
ns
TPLZ
Disable Time (Active to TRI-STATE) Low to Z, Figure 3
3.0
4.5
ns
TPZH
Enable Time (TRI-STATE to Active) Z to High, Figure 3
25.5 55.0
ns
TPZL
Enable Time (TRI-STATE to Active) Z to Low, Figure 3
25.5 55.0
ns
TLHT
Output Low-to-High Transition Time, 20% to 80%, Figure 5
290 400 580
ps
THLT
Output High-to-Low Transition Time, 80% to 20%, Figure 5
290 400 580
ps
TJIT
LVDS Data Path Peak to Peak Jitter, (Note VID = 300mV; 50% Duty Cycle; VCM =
6)
1.2V at 800Mbps
40
90
ps
TPLHD
TPHLD
TSKEW
TCCS
Propagation Low to High Delay, Figure 6
Propagation Low to High Delay, Figure 6
Propagation High to Low Delay, Figure 6
Propagation High to Low Delay, Figure 6
Pulse Skew |TPLHD - TPHLD|
Output Channel-to-Channel Skew, Figure 7
VID = 300mV; PRBS=223-1 data
pattern; VCM = 1.2V at 800Mbps
VCC = 3.3V, TA = 25°C
VCC = 3.3V, TA = 25°C
65
120
ps
0.9
1.3
1.6
ns
1.0
1.3
1.5
ns
0.9
1.3
1.6
ns
1.0
1.3
1.5
ns
0
225
ps
35
80
ps
Note 4: The parameters are guaranteed by design. The limits are based on statistical analysis of the device performance over PVT (process, voltage and
temperature) range.
Note 5: TSET and THOLD time specify that data must be in a stable state before and after the SEL transition.
Note 6: The parameters are guaranteed by design. The limits are based on statistical analysis of the device performance over PVT range with the following
equipment test setup: HP70004A (display mainframe) with HP70841B (pattern generator), 5 feet of RG-142 cable with DUT test board and HP83480A (digital
scope mainframe) with HP83483A (20GHz scope module).
3
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