DS90CP22 Datasheet, PDF (3/10 Pages) National Semiconductor (TI) – 2X2 800 Mbps LVDS Crosspoint Switch

AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified (Note 4)
Symbol
Parameter
Conditions
Min Typ Max Units
T_SET
Input to SEL Setup Time, Figures 1, 2
(Note 5)
0.7
0.5
ns
T_HOLD
Input to SEL Hold Time, Figures 1, 2
(Note 5)
1.0
0.5
ns
T_SWITCH
T_PHZ
T_PLZ
T_PZH
T_PZL
T_LHT
T_HLT
T_JIT
T_PLHD
T_PHLD
T_SKEW
T_CCS
SEL to Switched Output, Figures 1, 2
Disable Time (Active to TRI-STATE) High to Z, Figure 3
Disable Time (Active to TRI-STATE) Low to Z, Figure 3
Enable Time (TRI-STATE to Active) Z to High, Figure 3
Enable Time (TRI-STATE to Active) Z to Low, Figure 3
Output Low-to-High Transition Time, 20% to 80%, Figure 5
Output High-to-Low Transition Time, 80% to 20%, Figure 5
LVDS Data Path Peak to Peak Jitter,
(Note 6)
Propagation Low to High Delay, Figure 6
V_ID = 300mV; 50% Duty Cycle;
V_CM = 1.2V at 800Mbps
V_ID = 300mV; PRBS=2²³-1 data
pattern; V_CM = 1.2V at 800Mbps
Propagation Low to High Delay, Figure 6 V_CC = 3.3V, T_A = 25˚C
Propagation High to Low Delay, Figure 6
Propagation High to Low Delay, Figure 6 V_CC = 3.3V, T_A = 25˚C
Pulse Skew |T_PLHD - T_PHLD|
Output Channel-to-Channel Skew, Figure 7
0.9
1.2
1.7
ns
2.1
4.0
ns
3.0
4.5
ns
25.5 55.0
ns
25.5 55.0
ns
290 400 580
ps
290 400 580
ps
40
90
ps
75
190
ps
0.9
1.3
1.6
ns
1.0
1.3
1.5
ns
0.9
1.3
1.6
ns
1.0
1.3
1.5
ns
0
225
ps
35
80
ps
Note 4: The parameters are guaranteed by design. The limits are based on statistical analysis of the device performance over PVT (process, voltage and
temperature) range.
Note 5: T_SET and T_HOLD time specify that data must be in a stable state before and after the SEL transition.
Note 6: The parameters are guaranteed by design. The limits are based on statistical analysis of the device performance over PVT range with the following
equipment test setup: HP70004A (display mainframe) with HP70841B (pattern generator), 5 feet of RG-142 cable with DUT test board and HP83480A (digital scope
mainframe) with HP83483A (20GHz scope module).
3
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