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DS90CP22 Datasheet, PDF (1/10 Pages) National Semiconductor (TI) – 2X2 800 Mbps LVDS Crosspoint Switch
November 2003
DS90CP22
2X2 800 Mbps LVDS Crosspoint Switch
General Description
DS90CP22 is a 2x2 crosspoint switch utilizing LVDS (Low
Voltage Differential Signaling) technology for low power, high
speed operation. Data paths are fully differential from input
to output for low noise generation and low pulse width dis-
tortion. The non-blocking design allows connection of any
input to any output or outputs. LVDS I/O enable high speed
data transmission for point-to-point interconnects. This de-
vice can be used as a high speed differential crosspoint, 2:1
mux, 1:2 demux, repeater or 1:2 signal splitter. The mux and
demux functions are useful for switching between primary
and backup circuits in fault tolerant systems. The 1:2 signal
splitter and 2:1 mux functions are useful for distribution of
serial bus across several rack-mounted backplanes.
The DS90CP22 accepts LVDS signal levels, LVPECL levels
directly or PECL with attenuation networks.
The individual LVDS outputs can be put into TRI-STATE by
use of the enable pins.
For more details, please refer to the Application Information
section of this datasheet.
Features
n Low jitter 800 Mbps fully differential data path
n 75 ps (typ) of pk-pk jitter with PRBS = 223−1 data
pattern at 800 Mbps
n Single +3.3 V Supply
n Less than 330 mW (typ) total power dissipation
n Non-blocking "’Switch Architecture"’
n Balanced output impedance
n Output channel-to-channel skew is 35 ps (typ)
n Configurable as 2:1 mux, 1:2 demux, repeater or 1:2
signal splitter
n LVDS receiver inputs accept LVPECL signals
n Fast switch time of 1.2ns (typ)
n Fast propagation delay of 1.3ns (typ)
n Receiver input threshold < ±100 mV
n Available in 16 lead TSSOP and SOIC packages
n Inter-operates with ANSI/TIA/EIA-644-1995 LVDS
standard
n Operating Temperature: −40˚C to +85˚C
Connection Diagrams
10105305
Order Number DS90CP22M-8 (SOIC)
Order Number DS90CP22MT (TSSOP)
10105310
Diff. Output Eye-Pattern in 1:2 split mode @ 800 Mbps
Conditions: 3.3 V, PRBS = 223−1 data pattern,
VID = 300mV, VCM = +1.2 V, 200 ps/div, 100 mV/div
© 2003 National Semiconductor Corporation DS101053
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