DS90C032B_03 Datasheet, PDF (3/9 Pages) National Semiconductor (TI) – LVDS Quad CMOS Differential Line Receiver

Switching Characteristics
V_CC = +5.0V, T_A = +25˚C (Notes 3, 4, 9)
Symbol
Parameter
t_PHLD
t_PLHD
t_SKD
t_SK1
t_TLH
t_THL
t_PHZ
t_PLZ
t_PZH
t_PZL
Differential Propagation Delay High to Low
Differential Propagation Delay Low to High
Differential Skew |t_PHLD − t_PLHD|
Channel-to-Channel Skew (Note 5)
Rise Time
Fall Time
Disable Time High to Z
Disable Time Low to Z
Enable Time Z to High
Enable Time Z to Low
Conditions
Min Typ Max Units
C_L = 5 pF
1.5 3.40 5.0 ns
V_ID = 200 mV
1.5 3.48 5.0 ns
(Figure 1 and Figure 2) 0
80 600 ps
0
0.6 1.0 ns
0.5 2.0 ns
0.5 2.0 ns
R_L = 2 kΩ
C_L = 10 pF
(Figure 3 and Figure 4)
10
15
ns
10
15
ns
4
10
ns
4
10
ns
Switching Characteristics
V_CC = +5.0V ± 10%, T_A = −40˚C to +85˚C (Notes 3, 4, 9)
Symbol
Parameter
t_PHLD
t_PLHD
t_SKD
t_SK1
t_SK2
t_TLH
t_THL
t_PHZ
t_PLZ
t_PZH
t_PZL
Differential Propagation Delay High to Low
Differential Propagation Delay Low to High
Differential Skew |t_PHLD − t_PLHD|
Channel-to-Channel Skew (Note 5)
Chip to Chip Skew (Note 6)
Rise Time
Fall Time
Disable Time High to Z
Disable Time Low to Z
Enable Time Z to High
Enable Time Z to Low
Conditions
Min Typ Max Units
C_L = 5 pF
1.0 3.40 6.0 ns
V_ID = 200 mV
1.0 3.48 6.0 ns
(Figure 1 and Figure 2) 0 0.08 1.2 ns
0
0.6 1.5 ns
5.0 ns
0.5 2.5 ns
0.5 2.5 ns
R_L = 2 kΩ
C_L = 10 pF
(Figure 3 and Figure 4)
10
20
ns
10
20
ns
4
15
ns
4
15
ns
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground unless otherwise
specified.
Note 3: All typicals are given for: V_CC = +5.0V, T_A = +25˚C.
Note 4: Generator waveform for all tests unless otherwise specified: f = 1 MHz, Z_O = 50Ω, t_r and t_f (0%–100%) ≤ 1 ns for R_IN and t_r and t_f ≤ 6 ns for EN or EN*.
Note 5: Channel-to-Channel Skew is defined as the difference between the propagation delay of one channel and that of the others on the same chip with an event
on the inputs.
Note 6: Chip to Chip Skew is defined as the difference between the minimum and maximum specified differential propagation delays.
Note 7: ESD Rating:
HBM (1.5 kΩ, 100 pF) ≥ 2kV
EIAJ (0Ω, 200 pF) ≥ 250V
Note 8: Output short circuit current (I_OS) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time, do not
exceed maximum junction temperature specification.
Note 9: C_L includes probe and jig capacitance.
Parameter Measurement Information
10099003
FIGURE 1. Receiver Propagation Delay and Transition Time Test Circuit
3
www.national.com