DS90C032B_03 Datasheet, PDF (1/9 Pages) National Semiconductor (TI) – LVDS Quad CMOS Differential Line Receiver

September 2003
DS90C032B
LVDS Quad CMOS Differential Line Receiver
General Description
TheDS90C032B is a quad CMOS differential line receiver
designed for applications requiring ultra low power dissipa-
tion and high data rates. The device is designed to support
data rates in excess of 155.5 Mbps (77.7 MHz) utilizing Low
Voltage Differential Signaling (LVDS) technology.
TheDS90C032B accepts low voltage (350 mV) differential
input signals and translates them to CMOS (TTL compatible)
output levels. The receiver supports a TRI-STATE^® function
that may be used to multiplex outputs. The receiver also
supports OPEN Failsafe and terminated (100Ω) input Fail-
safe with the addition of external failsafe biasing. Receiver
output will be HIGH for both Failsafe conditions.
The DS90C032Bprovides power-off high impedance LVDS
inputs. This feature assures minimal loading effect on the
LVDS bus lines when V_CC is not present.
The DS90C032Band companion line driver (DS90C031B)
provide a new alternative to high power pseudo-ECL devices
for high speed point-to-point interface applications.
Features
n >155.5 Mbps (77.7 MHz) switching rates
n Accepts small swing (350 mV) differential signal levels
n High Impedance LVDS inputs with power down
n Ultra low power dissipation
n 600 ps maximum differential skew (5V, 25˚C)
n 6.0 ns maximum propagation delay
n Industrial operating temperature range
n Available in surface mount packaging (SOIC)
n Pin compatible with DS26C32A, MB570 (PECL) and
41LF (PECL)
n Supports OPEN and terminated input failsafe
n Conforms to ANSI/TIA/EIA-644 LVDS standard
Connection Diagram
Dual-In-Line
Functional Diagram
10099001
Order Number
DS90C032BTM
See NS Package
Number M16A
Receiver Truth Table
ENABLES
EN
EN*
L
H
All other
combinations
of ENABLE
inputs
TRI-STATE^® is a registered trademark of National Semiconductor Corporation.
© 2003 National Semiconductor Corporation DS100990
10099002
INPUTS
R_IN+ − R_IN−
X
V_ID ≥ 0.1V
V_ID ≤ −0.1V
Failsafe OPEN
or Terminated
OUTPUT
R_OUT
Z
H
L
H
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