CD4066BM Datasheet, PDF (3/8 Pages) National Semiconductor (TI) – Quad Bilateral Switch

DC Electrical Characteristics (Continued) CD4066BC (Note 2)
Symbol
Parameter
Conditions
b40 C
a25 C
a85 C
Units
Min Max Min Typ Max Min Max
SIGNAL INPUTS AND OUTPUTS
R_ON
‘‘ON’’ Resistance
DR_ON
D‘‘ON’’ Resistance
Between Any 2 of
4 Switches
I_IS
Input or Output Leakage
Switch ‘‘OFF’’
R_Le10
kX
to
V_DDbV_SS
2
V_CeV_DD V_SS to V_DD
V_DDe5V
V_DDe10V
V_DDe15V
R_Le10
kX
to
V_DDbV_SS
2
V_CCeV_DD V_ISeV_SS to V_DD
V_DDe10V
V_DDe15V
V_Ce0
850
330
210
g50
270 1050
120 400
80
240
1200 X
520 X
300 X
10
5
g0 1
g50
X
X
g200 nA
CONTROL INPUTS
V_ILC
V_IHC
I_IN
Low Level Input Voltage
High Level Input Voltage
Input Current
V_ISeV_SS and V_DD
V_OSeV_DD and V_SS
I_ISe g10mA
V_DDe5V
V_DDe10V
V_DDe15V
V_DDe5V
V_DDe10V (See note 6)
V_DDe15V
V_DDbV_SSe15V
V_DD^tV_IS^tV_SS
V_DD^tV_C^tV_SS
15
2 25 1 5
15
V
30
45
30
30
V
40
6 75 4 0
40
V
35
3 5 2 75
35
V
70
70 55
70
V
11 0
11 0 8 25
11 0
V
g0 3
g10^b5 g0 3
g1 0 mA
AC Electrical Characteristics T_Ae25 C t_ret_fe20 ns and V_SSe0V unless otherwise noted
Symbol
Parameter
Conditions
Min Typ Max
t_PHL t_PLH
t_PZH t_PZL
t_PHZ t_PLZ
Propagation Delay Time Signal
Input to Signal Output
Propagation Delay Time
Control Input to Signal
Output High Impedance to
Logical Level
Propagation Delay Time
Control Input to Signal
Output Logical Level to
High Impedance
Sine Wave Distortion
Frequency Response-Switch
‘‘ON’’ (Frequency at b3 dB)
V_CeV_DD C_Le50 pF (Figure 1 )
R_Le200k
V_DDe5V
V_DDe10V
V_DDe15V
R_Le1 0 kX C_Le50 pF (Figures 2 and 3 )
V_DDe5V
V_DDe10V
V_DDe15V
R_Le1 0 kX C_Le50 pF (Figures 2 and 3 )
V_DDe5V
V_DDe10V
V_DDe15V
V_CeV_DDe5V V_SSeb5V
R_Le10 kX V_ISe5V_p-p fe1 kHz
(Figure 4 )
V_CeV_DDe5V V_SSeb5V
R_Le1 kX V_ISe5V_p-p
20 Log₁₀ V_OS V_OS (1 kHz)bdB
(Figure 4 )
25
55
15
35
10
25
125
60
50
125
60
50
01
40
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
MHz
3