CD40192BM Datasheet, PDF (3/6 Pages) National Semiconductor (TI) – Synchronous 4-Bit Up/Down Decade Counter

DC Electrical Characteristics CD40192BC CD40193BC (Note 2) (Continued)
Symbol
I_OH
I_IN
Parameter
High Level Output
Current (Note 3)
Input Current
Conditions
V_DD e 5V V_O e 4 6V
V_DD e 10V V_O e 9 5V
V_DD e 15V V_O e 13 5V
V_DD e 15V V_IN e 0V
V_DD e 15V V_IN e 15V
b40 C
Min Max
b0 52
b1 3
b3 6
b0 3
03
Min
b0 44
b1 1
b3 0
a25 C
Typ
b0 88
b2 25
b8 8
b10^b5
10^b5
Max
b0 3
03
a85 C
Min Max
b0 36
b0 9
b2 4
b1 0
10
Units
mA
mA
mA
mA
mA
AC Electrical Characteristics
T_A e 25 C C_L e 50 pF R_L e 200 kX input t_r e t_f e 20 ns unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t_PHL or t_PLH
Propagation Delay Time
from Count Up or
Count Down to Q
V_DD e 5V
V_DD e 10V
V_DD e 15V
250
400
100
160
80
130
t_PHL or t_PLH
Propagation Delay Time
from Count Up to Carry
V_DD e 5V
V_DD e 10V
V_DD e 15V
120
200
50
80
40
65
t_PHL or t_PLH
Propagation Delay Time
from Count Down
to Borrow
V_DD e 5V
V_DD e 10V
V_DD e 15V
120
200
50
80
40
65
t_SU
Time Prior to Load
That Data Must
Be Present
V_DD e 5V
V_DD e 10V
V_DD e 15V
100
160
30
50
25
40
t_PHL
Propagation Delay Time
from Clear to Q
V_DD e 5V
V_DD e 10V
V_DD e 15V
130
220
60
100
50
80
t_PLH or t_PHL
Propagation Delay Time
from Load to Q
V_DD e 5V
V_DD e 10V
V_DD e 15V
300
480
120
190
95
150
t_TLH or t_THL
Output Transition Time
V_DD e 5V
V_DD e 10V
V_DD e 15V
100
200
50
100
40
80
f_CL
Maximum Count Frequency
V_DD e 5V
25
4
V_DD e 10V
6
10
V_DD e 15V
75
12 5
t_rCL or t_fCL
Maximum Count Rise
or Fall Time
V_DD e 5V
15
V_DD e 10V
5
V_DD e 15V
1
t_WH t_WL
Minimum Count Pulse
Width
V_DD e 5V
V_DD e 10V
V_DD e 15V
120
200
35
80
28
65
t_WH
Minimum Clear
Pulse Width
V_DD e 5V
V_DD e 10V
V_DD e 15V
300
480
120
190
95
150
t_WL
Minimum Load
Pulse Width
V_DD e 5V
V_DD e 10V
V_DD e 15V
100
160
40
65
32
55
C_IN
Average Input Capacitance
Load and Data
Inputs (A B C D)
Count Up Count
Down and Clear
5
75
10
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
ms
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
C_PD
Power Dissipation Capacity
(Note 4)
100
pF
AC Parameters are guaranteed by DC correlated testing
Note 1 ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed They are not meant to imply that the devices
should be operated at these limits The table of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provides conditions for actual device
operation
Note 2 V_SS e 0V unless otherwise specified
Note 3 I_OH and I_OL are tested one output at a time
Note 4 C_PD determines the no load AC power consumption of any CMOS device For complete explanation see 54C 74C Family Characteristics application note
AN-90
3