CD4014BM Datasheet, PDF (3/6 Pages) National Semiconductor (TI) – 8-Stage Static Shift Register

DC Electrical Characteristics CD4014BC (Note 2) (Continued)
Symbol
I_OH
I_IN
Parameter
High Level Output
Current (Note 3)
Input Current
Conditions
V_DD e 5V V_O e 4 6V
V_DD e 10V V_O e 9 5V
V_DD e 15V V_O e 13 5V
V_DD e 15V V_IN e 0V
V_DD e 15V V_IN e 15V
b40 C
Min Max
b0 52
b1 3
b3 6
b0 3
03
Min
b0 44
b1 1
b3 0
a25 C
Typ
b0 88
b2 2
b8
b10^b5
10^b5
Max
b0 3
03
a85 C
Min Max
b0 36
b0 90
b2 4
b1 0
10
Units
mA
mA
mA
mA
mA
AC Electrical Characteristics T_A e 25 C input t_r t_f e 20 ns C_L e 50 pF R_L e 200 kX
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t_PHL t_PLH
Propagation Delay Time
V_DD e 5V
V_DD e 10V
V_DD e 15V
200
320
ns
80
160
ns
60
120
ns
t_THL t_TLH
Transition Time
V_DD e 5V
V_DD e 10V
V_DD e 15V
100
200
ns
50
100
ns
40
80
ns
f_CL
Maximum Clock
Input Frequency
V_DD e 5V
28
4
V_DD e 10V
6
12
V_DD e 15V
8
16
MHz
MHz
MHz
t_W
Minimum Clock
Pulse Width
V_DD e 5V
V_DD e 10V
V_DD e 15V
90
180
ns
40
80
ns
25
50
ns
t_rCL t_fCL
Clock Rise and
Fall Time (Note 4)
V_DD e 5V
V_DD e 10V
V_DD e 15V
15
ms
15
ms
15
ms
t_S
Minimum Set-Up Time
(Note 6) Serial Input
t_H ^t 200 ns
V_DD e 5V
V_DD e 10V
V_DD e 15V
60
120
ns
40
80
ns
30
60
ns
Parallel Inputs
t_H ^t 200 ns
V_DD e 5V
V_DD e 10V
V_DD e 15V
80
160
ns
40
80
ns
30
60
ns
Parallel Serial Control
t_H ^t 200 ns
V_DD e 5V
V_DD e 10V
V_DD e 15V
100
200
ns
50
100
ns
40
80
ns
t_H
Minimum Hold Time
V_DD e 5V
Serial In Parallel In t_S ^t 400 ns
V_DD e 10V
Parallel Serial Control
V_DD e 15V
0
ns
10
ns
15
ns
C_I
Average Input Capacitance
Any Input
(Note 5)
5
75
pF
C_PD
Power Dissipation Capacitance
(Note 5)
110
pF
AC Parameters are guaranteed by DC correlated testing
Note 1 ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation
Note 2 V_SS e 0V unless otherwise specified
Note 3 I_OL and I_OH are tested one output at a time
Note 4 If more than one unit is cascaded t_rCL should be made less than or equal to the fixed propagation delay of the output of the driving stage for the estimated
capacitive load
Note 5 C_PD determines the no load AC power consumption of any CMOS device For complete explanation see 54C 74C family characteristics application note
AN-90
Note 6 Setup times are measured with reference to clock and a fixed hold time (t_H) as specified
3