CD4014BM Datasheet, PDF (1/6 Pages) National Semiconductor (TI) – 8-Stage Static Shift Register

February 1988
CD4014BM CD4014BC 8-Stage Static Shift Register
General Description
The CD4014BM CD4014BC is an 8-stage parallel input se-
rial output shift register A parallel serial control input en-
ables individual JAM inputs to each of 8 stages Q outputs
are available from the sixth seventh and eighth stages All
outputs have equal source and sink current capabilities and
conform to standard ‘‘B’’ series output drive
When the parallel serial control input is in the logical ‘‘0’’
state data is serially shifted into the register synchronously
with the positive transition of the clock When the parallel
serial control input is in the logical ‘‘1’’ state data is jammed
into each stage of the register synchronously with the posi-
tive transition of the clock
All inputs are protected against static discharge with diodes
to V_DD and V_SS
Features
Y _{Wide supply voltage range}
3 0V to 15V
Y _{High noise immunity}
Y _{Low power TTL}
compatibility
0 45 V_DD (typ )
Fan out of 2 driving 74L
or 1 driving 74LS
Y _{5V – 10V – 15V parametric ratings}
Y _{Symmetrical output characteristics}
Y _{Maximum input leakage}
1 mA at 15V over full temperature range
Connection Diagram
Dual-In-Line Package
Truth Table
Parallel
Serial
Q1
CL
Input
Serial
PI 1 PI n
(Internal)
Q_n
Control
LX
1
00
0
0
LX
1
10
1
0
LX
1
01
0
1
LX
1
11
1
1
L0
0
L1
0
KX
X
Level change
X e Don’t care case
XX
XX
XX
0
Q_nb₁
1
Q_nb₁
Q1
Q_{n No Change}
Order Number CD4014B
Top View
Logic Diagram
TL F 5947 – 1
C1995 National Semiconductor Corporation TL F 5947
TL F 5947 – 2
RRD-B30M105 Printed in U S A