96L02 Datasheet, PDF (3/6 Pages) National Semiconductor (TI) – Dual Retriggerable Resettable Monostable Multivibrator

Switching Characteristics V_CC e a5 0V T_A e a25 C
Symbol
Parameter
Conditions
t_PLH
Propagation Delay I0 to Q
V_CC e 5 0V R_X e 20 kX
I1 to Q
C_X e 0 C_L e 15 pF
t_PHL
Propagation Delay I0 to Q
V_CC e 5 0V R_X e 20 kX
I1 to Q
C_X e 0 C_L e 15 pF
t_PLH
t_PHL
Propagation Delay CD to Q
CD to Q
V_CC e 5 0V R_X e 39 kX
C_X e 1000 pF
96L02 (Mil)
Min Max
75
62
100
Functional Block Diagram
DM96L02 (Com)
Min
Max
80
65
Units
ns
ns
ns
Operation Notes
1 TRIGGERING can be accomplished by a positive-going
transition on pin 4 (12) or a negative-going transition on
pin 5 (11) Triggering begins as a signal crosses the input
V_IL V_IH threshold region this activates an internal latch
whose unbalanced cross-coupling causes it to assume a
preferred state As the latch output goes LOW it disables
the gates leading to the Q output and through an invert-
er turns on the capacitor discharge transistor The invert-
ed signal is also fed back to the latch input to change its
state and effectively end the triggering action thus the
latch and its associated feed-back perform the function of
a differentiator
The emitters of the latch transistors return to ground
through an enabling transistor which must be turned off
between successive triggers in order for the latch to pro-
ceed through the proper sequence when triggering is de-
sired Pin 5 (11) must be HIGH in order to trigger at pin 4
(12) conversely pin 4 (12) must be LOW in order to trig-
ger at pin 5 (11)
2 RETRIGGERING In a normal cycle triggering initiates a
rapid discharge of the external timing capacitor followed
by a ramp voltage run-up at pin 2 (14) The delay will time
out when the ramp voltage reaches the upper trigger
point of a Schmitt circuit causing the outputs to revert to
the quiescent state If another trigger occurs before the
ramp voltage reaches the Schmitt threshold the capaci-
tor will be discharged and the ramp will start again without
having disturbed the output The delay period can there-
fore be extended for an arbitrary length of time by insur-
ing that the interval between triggers is less than the de-
lay time as determined by the external capacitor and re-
sistor
3 NON-RETRIGGERABLE OPERATION Retriggering can
be inhibited logically by connecting pin 6 (10) back to pin
4 (12) or by connecting pin 7 (9) back to pin 5 (11) Either
hook-up has the effect of keeping the latch-enabling tran-
sistor turned on during the delay period which prevents
the input latch from cycling as discussed above in the
section on triggering
TL F 10203 – 3
4 OUTPUT PULSE WIDTH An external resistor R_X and an
external capacitor C_X are required as shown in the func-
tional block diagram To minimize stray capacitance and
noise pickup R_X and C_X should be located as close as
possible to the circuit In applications which require re-
mote trimming of the pulse width as with a variable resis-
tor R_X should consist of a fixed resistor in series with the
variable resistor the fixed resistor should be located as
close as possible to the circuit The output pulse width t_w
is defined as follows where R_X is in kX C_X is in pF and
t_w is in ns
t_w e 0 33 R_XC_X (1 a 3 R_X) for C_X ^t 10³ pF
16 kX ^s R_X ^s 220 kX for 0 C to a75 C
20 kX ^s R_X ^s 100 kX for b55 C to a125 C
C_X may vary from 0 to any value For pulse widths with C_X
less than 10³ pF see Figure a
5 SETUP AND RELEASE TIMES The setup times listed
below are necessary to allow the latch-enabling transistor
to turn off and the node voltages within the input latch to
stabilize thus insuring proper cycling of the latch when
the next trigger occurs The indicated release times
(equivalent to trigger duration) allow time for the input
latch to cycle and its signal to propagate
Input to Pin 5 (11)
Pin 4 (12) e L
Pin 3 (13) e H
TL F 10203 – 4
3