9308 Datasheet, PDF (3/6 Pages) National Semiconductor (TI) – Dual 4-Bit Latch

Functional Description
Data can be entered into the latch when both of the enable
inputs are LOW As long as this logic condition exists the
output of the latch will follow the input If either of the enable
inputs goes HIGH the data present in the latch at that time
is held in the latch and is no longer affected by data input
The master reset overrides all other input conditions and
forces the outputs of all the latches LOW when a LOW sig-
nal is applied to the Master Reset input
Logic Diagram
Truth Table
MR E0 E1 D
H
L
L
L
H
L
L
H
H
L
H
X
H
H
L
X
H
H
H
X
L
X
X
X
Q_nb₁ e Previous Output State
Q_n e Present Output State
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
Qn
L
H
Qnb1
Qnb1
Qnb1
L
Operation
Data Entry
Data Entry
Hold
Hold
Hold
Reset
TL F 10208 – 3
Switching Characteristics V_CC e a5 0V T_A e a25 C (See Section 5 for test waveforms and output load )
9308
Symbol
Parameter
C_L e 15 pF
R_L e 400X
Min
Max
Units
t_PLH
t_PHL
t_PLH
t_PHL
t_PHL
Propagation Delay
En to Qn
Propagation Delay
Dn to Qn
Propagation Delay
MR to Qn
30
ns
22
15
ns
18
22
ns
3