USBN9603 Datasheet, PDF (28/60 Pages) National Semiconductor (TI) – Universal Serial Bus Full Speed Function Controller with Enhanced DMA Support

6.0 Functional Description (Continued)
6.2.3 Programming Model
Figure 23 illustrates the register hierarchy for event reporting.
.
MAEV
FWEV
RXEV
TXEV
ALTEV
TXS0
TXC0
TXD0
RXS0
RXC0
RXD0
TXSx
TXCx
TXDx
RXSy
RXCx
RXDy
Figure 23. Register Hierarchy
NAKEV
EPC0
FIFO0
8 byte
EPCx
TFIFOx
64 byte
EPCy
RFIFOy
64 byte
6.3 POWER SAVING MODES
To minimize the power consumption of the USB node, the USBN9603 can be set to a static Halt mode. During Halt mode,
the clock oscillator circuit is disabled, stopping the external 24 MHz clock and 48 MHz frequency doubler, as well as the
clock output signal provided on the CLKOUT pin. However, all device internal status and register settings are preserved.
The device is set to Halt mode under the following conditions:
q _{If Halt On Suspend (HOS) is enabled (the HOS bit in the WKUP register is set to 1), the USBN9603 enters Halt mode}
when the node is set in Suspend state. Writing a 1 to HOS after the node is in Suspend state has no effect.
q _{If the node is not attached, the USBN9603 enters Halt mode, when the Force Halt bit (FHT) in the Wake-Up register}
is set to 1.
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