USBN9603 Datasheet, PDF (1/60 Pages) National Semiconductor (TI) – Universal Serial Bus Full Speed Function Controller with Enhanced DMA Support

- May 1998
PRELIMINARY
March 2000
USBN9603 Universal Serial Bus
Full Speed Function Controller with Enhanced DMA Support
General Description
The USBN9603 is an integrated, USB Node controller that
features enhanced DMA support with many automatic data
handling features. It is compatible with USB specification ver-
sions 1.0 and 1.1, and is an advanced version of the currently
available USBN9602.
A single IC integrates the required USB transceiver with a
3.3V regulator, a Serial Interface Engine (SIE), USB end-
point (EP) FIFOs, a versatile 8-bit parallel interface, a clock
generator and a MICROWIRE/PLUS™ interface. Seven
endpoint pipes are supported: one for the mandatory con-
trol endpoint and six to support interrupt, bulk and isochro-
nous endpoints. Each endpoint pipe has a dedicated FIFO,
8 bytes for the control endpoint and 64 bytes for the other
endpoints. The 8-bit parallel interface supports multiplexed
and non-multiplexed style CPU address/data buses. A pro-
grammable interrupt output scheme allows device configu-
ration for different interrupt signaling requirements.
Outstanding Features
q _{Low EMI, low standby current, 24 MHz oscillator}
q _{Advanced DMA mechanism}
q _{Fully static HALT mode with asynchronous wake-up}
for bus powered operation
q _{5V or 3.3V operation}
q _{Improved input range 3.3V signal voltage regulator}
q _{All unidirectional FIFOs are 64 bytes}
q _{Power-up reset and startup delay counter simplify sys-}
tem design
q _{Simple programming model controlled by external controller}
q _{Available in two packages}
— USBN9603SLB: small footprint for new designs and
portable applications
— USBN9603-28M: standard package, pin-to-pin com-
patible with USBN9602-28M
Block Diagram
CS RD WR A0/ALE D7-0/AD7-0 INTR MODE1-0
Microcontroller Interface
RESET
V_CC
GND
Endpoint/Control FIFOs
Serial Interface Engine (SIE)
Media Access Controller (MAC)
Physical Layer Interface (PHY)
24 MHz
Oscillator
Clock
Generator
Clock
Recovery
USB Event
Detect
Transceiver
VReg
D+ D- ^{Upstream Port}
XIN
XOUT
CLKOUT
V3.3
AGND
TRI-STATE^® is a registered trademark of National Semiconductor Corporation.
MICROWIRE/PLUS™ and MICROWIRE™ are trademarks of National Semiconductor Corporation.
© 2000 National Semiconductor Corporation
www.national.com