LP3921 Datasheet, PDF (28/34 Pages) National Semiconductor (TI) – Battery Charger Management and Regulator Unit with Integrated Boomer® Audio Amplifier

V_DD = 5V, R_L = 8Ω, and the system has DC coupled inputs
tied to ground.
TABLE 23. Feedback Resistor Mis-match
Tolerance R_F1 R_F2 V₀₂ - V₀₁
20%
0.8R 1.2R -0.500V
I_LOAD
62.5 mA
10%
0.9R 1.1R -0.250V
31.25 mA
5%
0.95R 1.05R -0.125V
15.63 mA
1%
0.99R 1.01R -0.025V
3.125 mA
0%
RR0
0
Similar results would occur if the input resistors were not
carefully matched. Adding input coupling capacitors in be-
tween the signal source and the input resistors will eliminate
this problem, however, to achieve best performance with min-
imum component count it is highly recommended that both
the feedback and input resistors matched to 1% tolerance or
better.
AUDIO POWER AMPLIFIER DESIGN
Design a 1W/8Ω Audio Amplifier
Given:
Power Output
1 Wrms
Load Impedance
Input Level
8Ω
1 Vrms
Input Impedance
20 kΩ
Bandwidth
100 Hz–20 kHz ± 0.25 dB
A designer must first determine the minimum supply rail to
obtain the specified output power. The supply rail can easily
be found by extrapolating from the Output Power vs Supply
Voltage graphs in the Typical Performance Characteris-
tics section. A second way to determine the minimum supply
rail is to calculate the required V_OPEAK using Equation 8 and
add the dropout voltages. Using this method, the minimum
supply voltage is (V_OPEAK + (V_{DO TOP} + (V_{DO BOT} )), where V_DO
BOT ^{and V}DO TOP ^{are extrapolated from the Dropout Voltage}
vs Supply Voltage curve in the Typical Performance Char-
acteristics section.
(8)
Using the Output Power vs. Supply Voltage graph for an 8Ω
load, the minimum supply rail just about 5V. Extra supply volt-
age creates headroom that allows the LP3921 to reproduce
peaks in excess of 1W without producing audible distortion.
At this time, the designer must make sure that the power sup-
ply choice along with the output impedance does not violate
the conditions explained in the Power Dissipation section.
Once the power dissipation equations have been addressed,
the required differential gain can be determined from Equa-
tion 9.
(9)
R_f / R_i = A_VD
(10)
From Equation 10, the minimum A_VD is 2.83. Since the de-
sired input impedance was 20 kΩ, a ratio of 2.83:1 of R_f to
R_i results in an allocation of R_i = 20 kΩ for both input resistors
and R_f = 60 kΩ for both feedback resistors. The final design
step is to address the bandwidth requirement which must be
stated as a single -3 dB frequency point. Five times away from
a -3 dB point is 0.17 dB down from pass band response which
is better than the required ±0.25 dB specified.
f_H = 20 kHz * 5 = 100 kHz
(11)
The high frequency pole is determined by the product of the
desired frequency pole, f_H , and the differential gain, A_VD. With
A_VD = 2.83 and f_H = 100 kHz, the resulting GBWP = 150 kHz
which is much smaller than the LP3921 GBWP of 10 MHz.
This figure displays that if a designer has a need to design an
amplifier with a higher differential gain, the LP3921 can still
be used without running into bandwidth limitations.
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