LP3921 Datasheet, PDF (23/34 Pages) National Semiconductor (TI) – Battery Charger Management and Regulator Unit with Integrated Boomer® Audio Amplifier

Further Charger Register
Information
CHARGER CONTROL REGISTER 1
TABLE 14. Register Address 8h'10: CHGCNTL1
BIT
NAME
FUNCTION (if bit = '1')
7 USB_MODE Sets the Current Level in USB
_EN
mode.
6 CHG_MODE Forces the charger into USB mode
_EN
when active high.
If low, charger is in normal charge
mode.
5
FORCE Forces an EOC event.
_EOC
4
TOUT_ Doubles the timeout delays for all
Doubling timeout signals.
3
EN_Tout Enables the timeout counters.
When set to '0' the timeout
counters are disabled.
2
EN_EOC Enables the End of Charge current
level threshold detection. When set
to '0' the functions are disabled.
1
Set_
Forces the charger into LDO mode.
LDOmode
0
EN_CHG Charger enable.
TABLE 15. Register Address 8h'13: CHGSTATUS1
BIT
NAME
FUNCTION (if bit = '1')
7 BAT_OVER Is set when battery voltage
_OUT
exceeds 4.7V.
6
CHGIN_ Is set when a valid input voltage is
OK_Out detected at CHG_IN pin.
5
EOC
Is set when the charging current
decreases below the programmed
End Of Charge level.
4
Tout_
Set after timeout on full rate
Fullrate charge.
3
Tout_
Set after timeout for precharge
Precharge mode.
2
LDO_Mode This bit is disabled in LP3921.
Contact NSC sales if this option is
required as in LP3918–L.
1
Fullrate Set when the charger is in CC/CV
mode.
0
PRECHG Set during precharge.
Charger Status Register 2 Read only
TABLE 16. Register Address 8h'13: CHGSTATUS2
BIT
NAME
FUNCTION (if bit = '1')
1 Tout_ConstV Set after timeout in CV phase.
0 BAD_BATT Set at bad battery state.
IMON CHARGE CURRENT MONITOR
Charge current is monitored within the charger section and a
proportional voltage representation of the charge current is
presented at the IMON output pin. The output voltage rela-
tionship to the actual charge current is represented in the
following graph and by the equation:
V_IMON(mV) = (2.47 x I_CHG)(mA)
30069811
FIGURE 7. IMON Voltage vs. Charge Current
Note that this function is not available if there is no input at
CHG_IN or if the charger is off due to the input at CHG_IN
being less than the compliance voltage.
LDO Information
OPERATIONAL INFORMATION
The LP3921 has 7 LDO's of which 3 are enabled by default,
LDO's 1,2 and 3 are powered up during the power up se-
quence. LDO's 4, 5 and 6 are separately, externally enabled
and will follow LDO2 in start up if their respective enable pin
is pulled high. LDO2, LDO3 and LDO7 can be enabled/dis-
abled via the serial interface.
LDO2 must remain in regulation otherwise the device will
power down. While LDO1 is enabled this must also be in reg-
ulation for the device to remain powered. If LDO1 is disabled
via I²C interface the device will not shut down.
INPUT VOLTAGES
There are two input voltage pins used to power the 7 LDO's
on the LP3921. V_IN2is the supply for LDO3, LDO4, LDO5,
LDO6 and LDO7. V_IN1is the supply for LDO1 and LDO2.
PROGRAMMING INFORMATION
Enable via Serial Interface
TABLE 17. Register Address 8h'00: OP_EN
BIT
NAME
FUNCTION
0
LDO1_EN Bit set to '0' - LDO disabled
2
LDO3_EN ^{Bit set to '1' - LDO enabled}
3
LDO7_EN
Note that the default setting for this Register is [0000 0101].
This shows that LDO1 and LDO3 are enabled by default
whereas LDO7 is not enabled by default on start up.
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