DP83640_08 Datasheet, PDF (25/124 Pages) National Semiconductor (TI) – Precision PHYTER - IEEE® 1588 Precision Time Protocol Transceiver

This interface may be used to connect PHY devices to a MAC
in 10/100 Mb/s systems. This section describes the nibble
wide MII data interface.
The nibble wide MII data interface consists of a receive bus
and a transmit bus each with control signals to facilitate data
transfer between the PHY and the upper layer (MAC).
10.1.1 Nibble-wide MII Data Interface
Clause 22 of the IEEE 802.3u specification defines the Media
Independent Interface. This interface includes a dedicated
receive bus and a dedicated transmit bus. These two data
buses, along with various control and status signals, allow for
the simultaneous exchange of data between the DP83640
and the upper layer agent (MAC).
The receive interface consists of a nibble wide data bus RXD
[3:0], a receive error signal RX_ER, a receive data valid flag
RX_DV, and a receive clock RX_CLK for synchronous trans-
fer of the data. The receive clock operates at either 2.5 MHz
to support 10 Mb/s operation modes or at 25 MHz to support
100 Mb/s operational modes.
The transmit interface consists of a nibble wide data bus TXD
[3:0], a transmit enable control signal TX_EN, and a transmit
clock TX_CLK which runs at either 2.5 MHz or 25 MHz.
Additionally, the MII includes the carrier sense signal CRS, as
well as a collision detect signal COL. The CRS signal asserts
to indicate the reception of data from the network or as a
function of transmit data in Half Duplex mode. The COL signal
asserts as an indication of a collision which can occur during
half-duplex operation when both a transmit and receive op-
eration occur simultaneously.
10.1.2 Collision Detect
For Half Duplex, a 10BASE-T or 100BASE-TX collision is de-
tected when the receive and transmit channels are active
simultaneously. Collisions are reported by the COL signal on
the MII.
If the DP83640 is transmitting in 10 Mb/s mode when a colli-
sion is detected, the collision is not reported until seven bits
have been received while in the collision state. This prevents
a collision being reported incorrectly due to noise on the net-
work. The COL signal remains set for the duration of the
collision.
If a collision occurs during a receive operation, it is immedi-
ately reported by the COL signal.
When heartbeat is enabled (only applicable to 10 Mb/s oper-
ation), approximately 1µs after the transmission of each pack-
et, a Signal Quality Error (SQE) signal of approximately 10 bit
times is generated (internally) to indicate successful trans-
mission. SQE is reported as a pulse on the COL signal of the
MII.
Collision is not indicated during Full Duplex operation.
10.1.3 Carrier Sense
In 10 Mb/s operation, Carrier Sense (CRS) is asserted due to
receive activity once valid data is detected via the Smart
Squelch function. During 100 Mb/s operation CRS is asserted
when a valid link (SD) and two non-contiguous zeros are de-
tected on the line.
For 10 or 100 Mb/s Half Duplex operation, CRS is asserted
during either packet transmission or reception.
For 10 or 100 Mb/s Full Duplex operation, CRS is asserted
only due to receive activity.
CRS is deasserted following an end of packet.
10.2 REDUCED MII INTERFACE
The DP83640 incorporates the Reduced Media Independent
Interface (RMII) as specified in the RMII specification (rev 1.2)
from the RMII Consortium. This interface may be used to
connect PHY devices to a MAC in 10/100 Mb/s systems using
a reduced number of pins. In this mode, data is transferred 2-
bits at a time using the 50 MHz RMII_REF clock for both
transmit and receive. The following pins are used in RMII
mode:
— TX_EN
— TXD[1:0]
— RX_ER (optional for MAC)
— CRS/CRS_DV
— RXD[1:0]
— X1 (25 MHz in RMII Master mode, 50 MHz in RMII Slave
mode)
— RX_CLK, TX_CLK, CLK_OUT (50 MHz RMII reference
clock in RMII Master mode only)
In addition, the RMII mode supplies an RX_DV signal which
allows for a simpler method of recovering receive data without
having to separate RX_DV from the CRS_DV indication. This
is especially useful for systems which do not require CRS,
such as systems that only support full-duplex operation. This
signal is also useful for diagnostic testing where it may be
desirable to loop external Receive RMII data directly to the
transmitter.
The RX_ER output may be used by the MAC to detect error
conditions. It is asserted for symbol errors received during a
packet, False Carrier events, and also for FIFO underrun or
overrun conditions. Since the PHY is required to corrupt re-
ceive data on an error, a MAC is not required to use RX_ER.
Since the reference clock operates at 10 times the data rate
for 10 Mb/s operation, transmit data is sampled every 10
clocks. Likewise, receive data will be generated every 10th
clock so that an attached device can sample the data every
10 clocks.
RMII Slave mode requires a 50 MHz oscillator to be connect-
ed to the device X1 pin. A 50 MHz crystal is not supported.
RMII Master mode can use either a 25 MHz oscillator con-
nected to X1 or a 25 MHz crystal connected to X1 and X2.
To tolerate potential frequency differences between the 50
MHz reference clock and the recovered receive clock, the re-
ceive RMII function includes a programmable elasticity buffer.
The elasticity buffer is programmable to minimize propagation
delay based on expected packet size and clock accuracy.
This allows for supporting a range of packet sizes including
jumbo frames.
The elasticity buffer will force Frame Check Sequence errors
for packets which overrun or underrun the FIFO. Underrun
and overrun conditions can be reported in the RMII and By-
pass Register (RBR). Table 5 indicates how to program the
elasticity buffer FIFO (in 4-bit increments) based on expected
maximum packet size and clock accuracy. It assumes both
clocks (RMII Reference clock and far-end Transmitter clock)
have the same accuracy.
Packet lengths can be scaled linearly based on accuracy (+/-
25 ppm would allow packets twice as large). If the threshold
setting must support both 10 Mb and 100 Mb operation, the
setting should be made to support both speeds.
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