DP83640_08 Datasheet, PDF (24/124 Pages) National Semiconductor (TI) – Precision PHYTER - IEEE® 1588 Precision Time Protocol Transceiver

allows sampling of background data to provide a baseline for
analysis.
9.10.5 TDR Pulse Monitor
The TDR function monitors data from the Analog to Digital
Converter (ADC) to detect both peak values and values above
a programmable threshold. It can be programmed to detect
maximum or minimum values. In addition, it records the time,
in 8 ns intervals, at which the peak or threshold value first
occurs.
The TDR monitor implements a timer that starts when the
pulse is transmitted. A window may be enabled to qualify in-
coming data to look for response only in a desired range. This
is especially useful for eliminating the transmitted pulse, but
also may be used to look for multiple reflections.
9.10.6 TDR Control Interface
The TDR Control Interface is implemented in the Link Diag-
nostics Registers - Page 2 through TDR Control
(TDR_CTRL), address 16h and TDR Window (TDR_WIN),
address 17h. The following basic controls are:
• TDR Enable: Enable bit 15 of TDR_CTRL (16h) to allow
the TDR function. This bypasses normal operation and
gives control of the CD10 and CD100 block to the TDR
function.
• TDR Send Pulse: Enable bit 11 of TDR_CTRL (16h) to
send the TDR pulse and starts the TDR Monitor
The following transmit mode controls are available:
• Transmit Mode: Enables use of 10 Mb Link pulses from
the 10 Mb Common Driver or data pulses from the 100 Mb
Common Driver by enabling TDR_100 Mb, bit 14 of
TDR_CRTL (16h).
• Transmit Pulse Width: Bits [10:8] of TDR_CTRL (16h)
allows sending of 0 to 7 clock width pulses. Actual pulses
are dependent on the transmit mode. If the pulse width is
set to 0, then no pulse will be sent.
• Transmit Channel Select: The transmitter can send
pulses down either the transmit pair or the receive pair by
enabling bit 13 of TDR_CTRL (16h). Default value is to
select the transmit pair.
The following receive mode controls are available:
• Min/Max Mode Control: Bit 7 of TDR_CTRL (16h)
controls the TDR Monitor operation. In default mode, the
monitor will detect maximum (positive) values. In Min
Mode, the monitor will detect minimum (negative) values.
• Receive Channel Select: The receiver can monitor either
the transmit pair or the receive pair by enabling bit 12 of
TDR_CTRL (16h). Default value is to select the transmit
pair.
• Receive Window: The receiver can monitor receive data
within a programmable window using the TDR Window
Register (TDR_WIN), address 17h. The window is
controlled by two register values: TDR Start Window, bits
[15:8] of TDR_WIN (17h) and TDR Stop Window, bits [7:0]
of TDR_WIN (17h). The TDR Start Window indicates the
first clock to start sampling. The TDR Stop Window
indicates the last clock to sample. By default, the full
window is enabled, with Start set to 0 and Stop set to 255.
The window range is in 8 ns clock increments, so the
maximum window size is 2048 ns.
9.10.7 TDR Results
The results of a TDR peak and threshold measurement are
available in the TDR Peak Measurement Register
(TDR_PEAK), address 18h and TDR Threshold Measure-
ment Register (TDR_THR), address 19h. The threshold mea-
surement may be a more accurate method of measuring the
length of longer cables since it provides a better indication of
the start of the received pulse, rather than the peak value.
Software utilizing the TDR function should implement an al-
gorithm to send TDR pulses and evaluate results. Multiple
runs should be used to best qualify any received pulses as
multiple reflections could exist. In addition, when monitoring
the transmitting pair, the window feature should be used to
disqualify the transmitted pulse. Multiple runs may also be
used to average the values providing more accurate results.
Actual distance measurements are dependent on the velocity
of propagation of the cable. The delay value is typically on the
order of 4.6 to 4.9 ns/m.
9.11 BIST
The DP83640 incorporates an internal Built-in Self Test
(BIST) circuit to accommodate in-circuit testing or diagnos-
tics. The BIST circuit can be utilized to test the integrity of the
transmit and receive data paths. BIST testing can be per-
formed with the part in the internal loopback mode or exter-
nally looped back using a loopback cable fixture.
The BIST is implemented with independent transmit and re-
ceive paths, with the transmit block generating a continuous
stream of a pseudo random sequence. The user can select a
9 bit or 15 bit pseudo random sequence from the PSR_15 bit
in the PHY Control Register (PHYCR). The received data is
compared to the generated pseudo-random data by the BIST
Linear Feedback Shift Register (LFSR) to determine the BIST
pass/fail status.
The pass/fail status of the BIST is stored in the BIST status
bit in the PHYCR register. The status bit defaults to 0 (BIST
fail) and will transition on a successful comparison. If an error
(mis-compare) occurs, the status bit is latched and is cleared
upon a subsequent write to the Start/Stop bit.
For transmit VOD testing, the Packet BIST Continuous Mode
can be used to allow continuous data transmission by setting
the BIST_CONT_MODE, bit 5, of CDCTRL1 (1Bh).
The number of BIST errors can be monitored through the
BIST Error Count in the CDCTRL1 (1Bh), bits [15:8].
10.0 MAC Interface
The DP83640 supports several modes of operation using the
MII interface pins. The options are defined in the following
sections and include:
— MII Mode
— RMII Mode
— Single Clock MII Mode (SCMII)
In addition, the DP83640 supports the standard 802.3u MII
Serial Management Interface.
The modes of operation can be selected by strap options or
register control. For RMII Slave mode, it is recommended to
use the strap option since it requires a 50 MHz clock instead
of the normal 25 MHz.
In each of these modes, the IEEE 802.3 serial management
interface is operational for device configuration and status.
The serial management interface of the MII allows for the
configuration and control of multiple PHY devices, gathering
of status, error information, and the determination of the type
and capabilities of the attached PHY(s).
10.1 MII INTERFACE
The DP83640 incorporates the Media Independent Interface
(MII) as specified in Clause 22 of the IEEE 802.3u standard.
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