ADC14DS080_0712 Datasheet, PDF (24/28 Pages) National Semiconductor (TI) – Dual 14-Bit, 80 MSPS A/D Converter with Serial LVDS Outputs

FIGURE 11. Read Timing
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FIGURE 12. Write Timing
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Device Control Register, Address 0h
76 5 4 3 2
1
0
OM DLC DCS OF WAM PD_A PD_B
Reset State : 08h
Bits (7:6) Operational Mode
0 0 Normal Operation.
0 1 Test Output mode. A fixed test pattern
(10100110001110 msb->lsb) is sourced at the
data outputs.
1 0 Test Output mode. Data pattern defined by
user in registers 01h and 02h is sourced at data
outputs.
1 1 Reserved.
Bit 5
Data Lane Configuration. When this bit is set to '0',
the serial data interface is configured for dual-lane
mode where the data words are output on two data
outputs (SD1 and SD0) at half the rate of the
single-lane interface. When this bit is set to ‘1’,
serial data is output on the SD1 output only and
the SD0 outputs are held in a high-impedance
state
Bit 4
Duty Cycle Stabilizer. When this bit is set to '0' the
DCS is off. When this bit is set to ‘1’, the DCS is
on.
Bit 3
Bit 2
Bit 1
Bit 0
Output Data Format. When this bit is set to ‘1’ the
data output is in the “twos complement” form.
When this bit is set to ‘0’ the data output is in the
“offset binary” form.
Word Alignment Mode.
This bit must be set to '0' in the single-lane mode
of operation.
In dual-lane mode, when this bit is set to '0' the
serial data words are offset by half-word. This
gives the least latency through the device. When
this bit is set to '1' the serial data words are in
word-aligned mode. In this mode the serial data
on the SD1 lane is additionally delayed by one
CLK cycle. (Refer to Figure 3).
Power-Down Channel A. When this bit is set to '1',
Channel A is in power-down state and Normal
operation is suspended.
Power-Down Channel B. When this bit is set to '1',
Channel B is in power-down state and Normal
operation is suspended.
User Test Pattern Register 0, Address 1h
7 6 543210
Reserved User Test Pattern (13:8)
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