ADC14DS080_0712 Datasheet, PDF (21/28 Pages) National Semiconductor (TI) – Dual 14-Bit, 80 MSPS A/D Converter with Serial LVDS Outputs

graded noise performance. Loading any of these pins, other
than V_CMO may result in performance degradation.
The nominal voltages for the reference bypass pins are as
follows:
V_CMO = 1.5 V
V_RP = 2.0 V
V_RN = 1.0 V
2.3 OF/DCS Pin
Duty cycle stabilization and output data format are selectable
using this quad state function pin. When enabled, duty cycle
stabilization can compensate for clock inputs with duty cycles
ranging from 30% to 70% and generate a stable internal clock,
improving the performance of the part. With OF/DCS = V_A the
output data format is 2's complement and duty cycle stabi-
lization is not used. With OF/DCS = AGND the output data
format is offset binary and duty cycle stabilization is not used.
With OF/DCS = (2/3)*V_A the output data format is 2's com-
plement and duty cycle stabilization is applied to the clock. If
OF/DCS is (1/3)*V_A the output data format is offset binary and
duty cycle stabilization is applied to the clock. While the sense
of this pin may be changed "on the fly," doing this is not rec-
ommended as the output data could be erroneous for a few
clock cycles after this change is made.
Note: This signal has no effect when SPI_EN is high and the
serial control interface is enabled.
3.0 DIGITAL INPUTS
Digital CMOS compatible inputs consist of CLK, and PD_A,
PD_B, Reset_DLL, DLC, TEST, WAM, SPI_EN, SCSb,
SCLK, and SDI.
3.1 Clock Input
The CLK controls the timing of the sampling process. To
achieve the optimum noise performance, the clock input
should be driven with a stable, low jitter clock signal in the
range indicated in the Electrical Table. The clock input signal
should also have a short transition region. This can be
achieved by passing a low-jitter sinusoidal clock source
through a high speed buffer gate. The trace carrying the clock
signal should be as short as possible and should not cross
any other signal line, analog or digital, not even at 90°.
The clock signal also drives an internal state machine. If the
clock is interrupted, or its frequency is too low, the charge on
the internal capacitors can dissipate to the point where the
accuracy of the output data will degrade. This is what limits
the minimum sample rate.
The clock line should be terminated at its source in the char-
acteristic impedance of that line. Take care to maintain a
constant clock line impedance throughout the length of the
line. Refer to Application Note AN-905 for information on set-
ting characteristic impedance.
It is highly desirable that the the source driving the ADC clock
pins only drive that pin. However, if that source is used to drive
other devices, then each driven pin should be AC terminated
with a series RC to ground, such that the resistor value is
equal to the characteristic impedance of the clock line and the
capacitor value is
where t_PD is the signal propagation rate down the clock line,
"L" is the line length and Z_O is the characteristic impedance
of the clock line. This termination should be as close as pos-
sible to the ADC clock pin but beyond it as seen from the clock
source. Typical t_PD is about 150 ps/inch (60 ps/cm) on FR-4
board material. The units of "L" and t_PD should be the same
(inches or centimeters).
The duty cycle of the clock signal can affect the performance
of the A/D Converter. Because achieving a precise duty cycle
is difficult, the ADC14DS080 has a Duty Cycle Stabilizer.
3.2 Power-Down (PD_A and PD_B)
The PD_A and PD_B pins, when high, hold the respective
channel of the ADC14DS080 in a power-down mode to con-
serve power when that channel is not being used. The chan-
nels may be powereed down individually or together. The data
in the pipeline is corrupted while in the power down mode.
The Power Down Mode Exit Cycle time is determined by the
value of the components on the reference bypass pins
( V_RP, V_CMO and V_RN ). These capacitors loose their charge
in the Power Down mode and must be recharged by on-chip
circuitry before conversions can be accurate. Smaller capac-
itor values allow slightly faster recovery from the power down
mode, but can result in a reduction in SNR, SINAD and ENOB
performance.
Note: This signal has no effect when SPI_EN is high and the
serial control interface is enabled.
3.3 Reset_DLL
This pin is normally low. If the input clock frequency is
changed abruptly, the internal timing circuits may become
unlocked. Cycle this pin high for 1 microsecond to re-lock the
DLL. The DLL will lock in several microseconds after
Reset_DLL is asserted.
3.4 DLC
This pin sets the output data configuration. With this signal at
logic-1, all data is sourced on a single lane (SD1_x) for each
channel. When this signal is at logic-0, the data is sourced on
dual lanes (SD0_x and SD1_x) for each channel. This sim-
plifies data capture at higher data rates.
Note: This signal has no effect when SPI_EN is high and the
SPI interface is enabled.
3.5 TEST
When this signal is asserted high, a fixed test pattern
(10100110001110 msb->lsb) is sourced at the data outputs.
When low, the ADC is in normal operation. The user may
specify a custom test pattern via the serial control interface.
Note: This signal has no effect when SPI_EN is high and the
SPI interface is enabled.
3.6 WAM
In dual-lane mode only, when this signal is at logic-0 the serial
data words are offset by half-word. With this signal at logic-1
the serial data words are aligned with each other. In single
lane mode this pin must be set to logic-0.
Note: This signal has no effect when SPI_EN is high and the
SPI interface is enabled.
3.7 SPI_EN
The SPI interface is enabled when this signal is asserted high.
In this case the direct control pins (OF/DCS, PD_A, PD_B,
DLC, WAM, TEST) have no effect. When this signal is de-
asserted, the SPI interface is disabled and the direct control
pins are enabled.
21
www.national.com