ADC08500 Datasheet, PDF (24/34 Pages) National Semiconductor (TI) – High Performance, Low Power 8-Bit, 500 MSPS A/D Converter

TABLE 3. Register Addresses
4-Bit Address
Loading Sequence:
A3 loaded after H0, A0 loaded last
A3 A2 A1 A0 Hex Register Addressed
0
0
0
0
0h
Reserved
0
0
0
1
1h
Configuration
0
0
1
0
2h
Input Offset
0
0
1
1
3h
Input Full-Scale
Voltage Adjust
0
1
0
0
4h
Reserved
0
1
0
1
5h
Reserved
0
1
1
0
6h
Reserved
0
1
1
1
7h
Reserved
1
0
0
0
8h
Reserved
1
0
0
1
9h
Reserved
1
0
1
0
Ah
Reserved
1
0
1
1
Bh
Reserved
1
1
0
0
Ch
Reserved
1
1
0
1
Dh
Reserved
1
1
1
0
Eh
Reserved
1
1
1
1
Fh
Reserved
1.4 REGISTER DESCRIPTION
Three write-only registers provide several control and config-
uration options in the Extended Control Mode. These regis-
ters have no effect when the device is in the Normal Control
Mode. Each register description below also shows the Power-
On Reset (POR) state of each control bit.
Configuration Register
Addr: 1h (0001b)
W only (0xB2FF)
D15 D14 D13 D12 D11 D10 D9 D8
1 0 1 DCS DCP nDE OV OE
D7 D6 D5 D4 D3 D2 D1 D0
11111111
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Must be set to 1b
Must be set to 0b
Must be set to 1b
DCS: Duty Cycle Stabilizer. When this bit is set
to 1b, a duty cycle stabilization circuit is
applied to the clock input. When this bit is set
to 0b the stabilization circuit is disbaled.
DCP: DDR Clock Phase. This bit only has an
effect in the DDR mode. When this bit is set to
0b, the DCLK edges are time-aligned with the
data bus edges ("0° Phase"). When this bit is
set to 1b, the DCLK edges are placed in the
middle of the data bit-cells ("90° Phase"),
using the one-half speed DCLK shown in
Figure 4 as the phase reference.
POR State: 0b
Bit 10
Bit 9
Bit 8
Bits 7:0
nDE: DDR Enable. When this bit is set to 0b,
data bus clocking follows the DDR (Dual Data
Rate) mode whereby a data word is output
with each rising and falling edge of DCLK.
When this bit is set to a 1b, data bus clocking
follows the SDR (single data rate) mode
whereby each data word is output with either
the rising or falling edge of DCLK , as
determined by the OutEdge bit.
POR State: 0b
OV: Output Voltage. This bit determines the
LVDS outputs' voltage amplitude and has the
same function as the OutV pin that is used in
the normal control mode. When this bit is set
to 1b, the standard output amplitude of 710
mV_P-P is used. When this bit is set to 0b, the
reduced output amplitude of 510 mV_P-P is
used.
POR State: 1b
OE: Output Edge. This bit selects the DCLK
edge with which the data words transition in
the SDR mode and has the same effect as the
OutEdge pin in the normal control mode.
When this bit is 1b, the data outputs change
with the rising edge of DCLK+. When this bit is
0b, the data output change with the falling
edge of DCLK+.
POR State: 0b
Must be set to 1b.
Input Offset
Addr: 2h (0010b)
W only (0x007F)
D15 D14 D13 D12 D11 D10 D9 D8
(MSB)
Offset Value
(LSB)
D7 D6 D5 D4 D3 D2 D1 D0
Sign 1 1 1 1 1 1 1
Bits 15:8
Bit 7
Bit 6:0
Offset Value. The input offset of the I-Channel
ADC is adjusted linearly and monotonically by
the value in this field. 00h provides a nominal
zero offset, while FFh provides a nominal 45
mV of offset. Thus, each code step provides
0.176 mV of offset.
POR State: 0000 0000b
Sign bit. 0b gives positive offset, 1b gives
negative offset resulting in total offset
adjustment of ±45 mV.
POR State: 0b
Must be set to 1b
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