ADC08500 Datasheet, PDF (12/34 Pages) National Semiconductor (TI) – High Performance, Low Power 8-Bit, 500 MSPS A/D Converter

Specification Definitions
APERTURE (SAMPLING) DELAY is the amount of delay,
measured from the sampling edge of the CLK input, after
which the signal present at the input pin is sampled inside the
device.
APERTURE JITTER (t_AJ) is the variation in aperture delay
from sample to sample. Aperture jitter shows up as input
noise.
Bit Error Rate (B.E.R.) is the probability of error and is de-
fined as the probable number of word errors on the ADC
output per unit of time divided by the number of words seen
in that amount of time. A B.E.R. of 10^-18 corresponds to a
statistical error in one word about every four (4) years.
CLOCK DUTY CYCLE is the ratio of the time that the clock
wave form is at a logic high to the total time of one clock pe-
riod.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of
the maximum deviation from the ideal step size of 1 LSB.
Measured at sample rate = 500 MSPS with a 1MHz input
sinewave.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE
BITS) is another method of specifying Signal-to-Noise and
Distortion Ratio, or SINAD. ENOB is defined as (SINAD −
1.76) / 6.02 and says that the converter is equivalent to a per-
fect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH (FPBW) is a measure of the
frequency at which the reconstructed output fundamental
drops 3 dB below its low frequency value for a full scale input.
GAIN ERROR is the deviation from the ideal slope of the
transfer function. It can be calculated from Offset and Full-
Scale Errors:
Positive Gain Error = Offset Error − Positive Full-Scale
Error
Negative Gain Error = −(Offset Error − Negative Full-
Scale Error)
Gain Error = Negative Full-Scale Error − Positive Full-
Scale Error = Positive Gain Error + Negative Gain Error
INTEGRAL NON-LINEARITY (INL) is a measure of worst
case deviation of the ADC transfer function from an ideal
straight line drawn through the ADC transfer function. The
deviation of any given code from this straight line is measured
from the center of that code value step. The best fit method
is used.
INTERMODULATION DISTORTION (IMD) is the creation of
additional spectral components as a result of two sinusoidal
frequencies being applied to the ADC input at the same time.
It is defined as the ratio of the power in the second and third
order intermodulation products to the power in one of the
original frequencies. IMD is usually expressed in dBFS.
LSB (LEAST SIGNIFICANT BIT) is the bit that has the small-
est value or weight of all bits. This value is
V_FS / 2ⁿ
where V_FS is the differential full-scale amplitude V_IN as set by
the FSR input and "n" is the ADC resolution in bits, which is
8 for the ADC08500.
LVDS DIFFERENTIAL OUTPUT VOLTAGE (V_OD) is the ab-
solute value of the difference between the V_D+ & V_D- outputs;
each measured with respect to Ground.
FIGURE 1.
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LVDS OUTPUT OFFSET VOLTAGE (V_OS) is the midpoint
between the D+ and D- pins output voltage referenced to
ground. ie., [(V_D+) +( V_D-)]/2.
MISSING CODES are those output codes that are skipped
and will never appear at the ADC outputs. These codes can-
not be reached with any input value.
MSB (MOST SIGNIFICANT BIT) is the bit that has the largest
value or weight. Its value is one half of full scale.
NEGATIVE FULL-SCALE ERROR (NFSE) is a measure of
how far the first code transition is from the ideal 1/2 LSB above
a differential -V_IN/2. For the ADC08500 the reference voltage
is assumed to be ideal, so this error is a combination of full-
scale error and reference voltage error.
OFFSET ERROR (V_OFF) is a measure of how far the mid-
scale point is from the ideal zero voltage differential input.
Offset Error = Actual Input causing average of 8k sam-
ples to result in an average code of 127.5.
OUTPUT DELAY (t_OD) is the time delay after the falling edge
of DCLK before the data update is present at the output pins.
OVER-RANGE RECOVERY TIME is the time required after
the differential input voltages goes from ±1.2V to 0V for the
converter to recover and make a conversion with its rated ac-
curacy.
PIPELINE DELAY (LATENCY) is the number of clock cycles
between initiation of conversion and when that data is pre-
sented to the output driver stage. New data is available at
every clock cycle, but the data lags the conversion by the
Pipeline Delay plus the t_OD.
POSITIVE FULL-SCALE ERROR (PFSE) is a measure of
how far the last code transition is from the ideal 1-1/2 LSB
below a differential +V_IN/2 . For the ADC08500 the reference
voltage is assumed to be ideal, so this error is a combination
of full-scale error and reference voltage error.
POWER SUPPLY REJECTION RATIO (PSRR) can be one
of two specifications. PSRR1 (DC PSRR) is the ratio of the
change in full-scale error that results from a power supply
voltage change from 1.8V to 2.0V. PSRR2 (AC PSRR) is a
measure of how well an a.c. signal riding upon the power
supply is rejected from the output and is measured with a 248
MHz, 50 mV_P-P signal riding upon the power supply. It is the
ratio of the output amplitude of that signal at the output to its
amplitude on the power supply pin. PSRR is expressed in dB.
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in
dB, of the rms value of the input signal at the output to the rms
value of the sum of all other spectral components below one-
half the sampling frequency, not including harmonics or d.c.
SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or
SINAD) is the ratio, expressed in dB, of the rms value of the
input signal at the output to the rms value of all of the other
spectral components below half the clock frequency, includ-
ing harmonics but excluding d.c.
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