LMK04800_14 Datasheet, PDF (23/79 Pages) National Semiconductor (TI) – Low-Noise Clock Jitter Cleaner with Dual Loop PLLs

LMK048XX EVALUATION BOARD OPERATING INSTRUCTIONS
by the reference input of PLL2 now. The PLL2 reference frequency will remain at the VCXO
frequency.
When the PLL1 VCXO frequency is different from the PLL2 reference frequency, a warning
will be displayed on the clock outputs tab informing the user that PLL1 VCO and PLL2
reference frequency are mismatched and the one or more of the PLLs are out of lock. While
there still could be an error in the divider values which may cause a non-locked PLL, this
warning by itself may no longer be assumed true. It is up to the user to ensure the PLL dividers
are programmed correctly.
To illustrate the proper programming of the LMK04800 device in dual loop 0-delay mode the
following case examples are provided. Note that in one of the cases, the feedback frequency
from the clock output matches the VCXO frequency and CodeLoader will display the proper
frequency values.
Dual Loop 0-Delay (MODE=2 or 5) Case 1: For example the default configuration, 122.88 MHz
CLKin, 122.88 MHz VCXO, of the LMK04808 has the following register programming.
Case 1:
Default Mode
Actual PLL1
VCXO Frequency
Reported PLL1
VCXO Frequency
PLL1 N
Actual PLL2
VCO Frequency
Reported PLL2
VCO Frequency
PLL2_N
PLL2_P (Pre-N)
PLL2 VCO Divider
CLKout8 Divide
Actual CLKout8
Output Frequency
Reported CLKotu8
Output Frequency
No 0-Delay
122.88
122.88
120
2949.12 MHz
2949.12 MHz
12
2
Bypassed
12
245.76 MHz
245.76 MHz
Case2:
Default 0-Delay
Mode
(CLKout8 =
122.88 MHz)
122.88
Case 3:
Default 0-Delay
Mode (Updated
CLKout8 =
245.76 MHz)
Case 4:
Default 0-Delay
Mode (Updated
CLKout8 =
61.44 MHz)
122.88
122.88
122.88
120
2949.12 MHz
61.44
60
2949.12 MHz
245.76
240
2949.12 MHz
2949.12 MHz
12
2
Bypassed
24
122.88 MHz
2949.12 MHz
12
2
Bypassed
12
245.76 MHz
2949.12 MHz
12
2
Bypassed
48
61.44 MHz
122.88 MHz
245.76 MHz
61.44 MHz
23