LMK04800_14 Datasheet, PDF (14/79 Pages) National Semiconductor (TI) – Low-Noise Clock Jitter Cleaner with Dual Loop PLLs

LMK048XX EVALUATION BOARD OPERATING INSTRUCTIONS
Connector Name
Signal Type,
Input/Output
Description
Buffered outputs of OSCin port.
The output terminations on the evaluation board are
shown below, the output type selected by default in
CodeLoader is indicated by an asterisk (*):
OSC output pair
Default Board
Termination
OSCout0
LVDS* / LVCMOS
OSCout1
LVPECL* (fixed)
Populated:
OSCout0, OSCout0*,
OSCout1, OSCout1*
Analog,
Output
Only OSCout0 has a programmable LVDS, LVPECL,
or LVCMOS output buffer. The OSCout0 buffer type
can be selected in CodeLoader on the Clock Outputs
tab via the OSCout0_TYPE control. OSCout1 has
LVPECL buffer only but has programmable swing
amplitude.
Both OSCout pairs are AC-coupled to allow safe
testing with RF test equipment.
The OSCout1 output is source-terminated using 240-
ohm resistors.
If OSCout0 is programmed as LVCMOS, each output
can be independently configured (normal, inverted,
inverted, and off/tri-state).
Main power supply input for the evaluation board.
A 3.9 V DC power source applied to this SMA will, by
default, source the onboard LDO regulators that power
the inner layer planes that supply the LMK048xxB and
its auxiliary circuits (e.g. VCXO).
Vcc
Power,
Input
The LMK048xxB contains internal voltage regulators
for the VCO, PLL and other internal blocks. The clock
outputs do not have an internal regulator, so a clean
power supply with sufficient output current capability
is required for optimal performance.
On-board LDO regulators and 0 resistor options
provide flexibility to supply and route power to various
devices. See schematics for more details.
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