SCANSTA101_06 Datasheet, PDF (22/32 Pages) National Semiconductor (TI) – Low Voltage IEEE 1149.1 STA Master

TABLE 18. STA101 Scan Signal Descriptions
Signal Name
SCAN_EN
SCAN_IN
SCAN_OUT
No. of
Bits
1
1
1
Pin Type
I
I
O
Driver Type
Shared TRIST
Shared DATA15
Shared DATA14
Freq.
MHz
TBD
TBD
TBD
Description
STA101 Scan Enable Shared pin with TRIST.
STA101 Scan Data In. Shared pin with DATA15.
STA101 Scan Data Out. Shared pin with DATA14.
TEST AND DEBUG INTERFACE
The test and debug interfaces are provided to perform man-
ufacturing tests. There is a standard JTAG interface along
with a scan interface. The scan interface have shared pins
with the external data pins. Scan is selected by a user defined
instruction through the JTAG port. Note that the scan chain
(s) will not be hooked up to the JTAG tap.
SAFE MODE
This device implements the following design rules to provide
SEU/SEE protection:
• Triple modular redundancy for TRST0_SM and
TRST1_SM outputs with the help of a TMR D flip-flop .
• After reset all scan interface outputs are driven to SEU
tolerant safe values as shown below:
TMS_SM = 1
TCK_SM = 0
TDO_SM = Z
TRST0_SM = 0
TRST1_SM = 0
• The EXTEST and the HIGHZ outputs from the JTAG TAP
controller are gated with TRST to protect the boundary
scan cells from inadvertantly entering the test mode.
Software Interface Details
CLOCK GENERATION AND DISTRIBUTION
Input Clock (SCK): Up to 66 MHz
Output Clock (TCK_SM): TCK_SM is a divided, registered
version of SCK.
• Selectable: to 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, and 1/128 of
SCK.
• Frequency: up to 25 MHz
RESET STRATEGY
The incoming external hardware reset (RST) will be synchro-
nized to the incoming clock (SCK) and is combined with the
soft reset to generate a synchronized internal reset
(SYS_RST_N). During operation, the chip can be reset by
writing a '1' to the Reset bit in the Setup register. All logic
throughout the device will be initialized, all control and status
registers will be in a known default state, all PPI memory ad-
dress pointers will default to their respective base addresses,
the SSI memory pointer will default to zero, the Tap Tracker
will be reset to TLR, and the clock division counter will be
initialized to all zero's after deassertion of the internal reset.
The Reset bit in the Setup register is self clearing. The TRST
bit in the Setup register, when set, resets the SSI logic and
drives the TRST0_SM and TRST1_SM to zero.
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