SCANSTA101_06 Datasheet, PDF (1/32 Pages) National Semiconductor (TI) – Low Voltage IEEE 1149.1 STA Master

November 2006
SCANSTA101
Low Voltage IEEE 1149.1 STA Master
General Description
The SCANSTA101 is designed to function as a test master
for a IEEE 1149.1 test system. The minimal requirements to
create a tester are a microcomputer (uP, RAM/ROM, clock,
etc.), SCANEASE r2.0 software, and a STA101.
The SCANSTA101 is an enhanced version of, and replace-
ment for, the SCANPSC100. The additional features of the
STA101 further allow it to offload some of the processor over-
head while remaining flexible. The device architecture sup-
ports IEEE 1149.1, BIST, and IEEE 1532. The flexibility will
allow it to adapt to any changes that may occur in 1532 and
support yet unknown variants.
The SCANSTA101 is useful in improving vector throughput
when applying serial vectors to system test circuitry and re-
duces the software overhead that is associated with applying
serial patterns with a parallel processor. The SCANSTA101
features a generic Parallel Processor Interface (PPI) which
operates by serializing data from the parallel bus for shifting
through the chain of 1149.1 compliant components (i.e., scan
chain). Writes can be controlled either by wait states or the
DTACK line. Handshaking is accomplished with either polling
or interrupts.
Features
■ ^{Compatible with IEEE Std. 1149.1 (JTAG) Test Access}
Port and Boundary Scan Architecture
■ ^{Supported by National's SCAN Ease (Embedded}
Application Software Enabler) Software Rev 2.0
■ ^{Uses generic, asynchronous processor interface;}
compatible with a wide range of processors and PCLK
frequencies
■ ^{16-bit Data Interface (IP scalable to 32-bit)}
■ ^{2Kx32 bit dual-port memory addressing for access by the}
PPI or the 1149.1 master
■ ^{Load-on-the-fly (LotF) and Preload operating modes}
supported
■ ^{On-Board Sequencer allows multi-vector operations such}
as those required to load data into an FPGA
■ ^{On-Board Compares support TDI validation against}
preloaded expected data
■ ^{32-bit Linear Feedback Shift Register (LFSR) at the Test}
Data In (TDI) port
■ ^{State, Shift, and BIST macros allow predetermined TMS}
sequences to be utilized
■ ^{Operates at 3.3v supply voltages w/ 5V tolerant I/O}
■ ^{Outputs support Power-Down TRI-STATE mode.}
SCANSTA101 Architecture
FIGURE 1.
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