ADC12DL066_08 Datasheet, PDF (22/24 Pages) National Semiconductor (TI) – Dual 12-Bit, 66Msps, 450MHz Input Bandwidth A/D Converter w/Internal Reference

tional amplifier operated in the non-inverting configuration will
exhibit more time delay than will the same device operating
in the inverting configuration.
Operating with the reference pins outside of the specified
range. As mentioned in Section 1.2, V_REF should be in the
range of
0.8V ≤ V_REF ≤ 1.5V
Operating outside of these limits could lead to performance
degradation.
Inadequate network on Reference Bypass pins (V_RPA,
V_RNA, V_RMA, V_RPB, V_RNB and V_RMB). As mentioned in Sec-
tion 1.2, these pins should be bypassed with 0.1 µF capacitors
to ground at V_RMA and V_RMB and with a series RC of 1.5 Ω
and 1.0 µF between pins V_RPA and V_RNA and between V_RPB
and V_RNB for best performance.
Using a clock source with excessive jitter, using exces-
sively long clock signal trace, or having other signals
coupled to the clock signal trace. This will cause the sam-
pling interval to vary, causing excessive output noise and a
reduction in SNR and SINAD performance.
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