ADC12DL066_08 Datasheet, PDF (21/24 Pages) National Semiconductor (TI) – Dual 12-Bit, 66Msps, 450MHz Input Bandwidth A/D Converter w/Internal Reference

Since digital switching transients are composed largely of
high frequency components, total ground plane copper
weight will have little effect upon the logic-generated noise.
This is because of the skin effect. Total surface area is more
important than is total ground plane volume.
Generally, analog and digital lines should cross each other at
90° to avoid crosstalk. To maximize accuracy in high speed,
high resolution systems, however, avoid crossing analog and
digital lines altogether. It is important to keep clock lines as
short as possible and isolated from ALL other lines, including
other digital lines. Even the generally accepted 90° crossing
should be avoided with the clock line as even a little coupling
can cause problems at high frequencies. This is because oth-
er lines can introduce jitter into the clock line, which can lead
to degradation of SNR. Also, the high speed clock can intro-
duce noise into the analog chain.
Best performance at high frequencies and at high resolution
is obtained with a straight signal path. That is, the signal path
through all components should form a straight line wherever
possible.
Be especially careful with the layout of inductors. Mutual in-
ductance can change the characteristics of the circuit in which
they are used. Inductors should not be placed side by side,
even with just a small part of their bodies beside each other.
The analog input should be isolated from noisy signal traces
to avoid coupling of spurious signals into the input. Any ex-
ternal component (e.g., a filter capacitor) connected between
the converter's input pins and ground or to the reference input
pin and ground should be connected to a very clean point in
the ground plane.
Figure 6 gives an example of a suitable layout. All analog cir-
cuitry (input amplifiers, filters, reference components, etc.)
should be placed in the analog area of the board. All digital
circuitry and I/O lines should be placed in the digital area of
the board. The ADC12DL066 should be between these two
areas. Furthermore, all components in the reference circuitry
and the input signal chain that are connected to ground should
be connected together with short traces and enter the ground
plane at a single, quiet point. All ground connections should
have a low inductance path to ground.
6.0 DYNAMIC PERFORMANCE
To achieve the best dynamic performance, the clock source
driving the CLK input must be free of jitter. Isolate the ADC
clock from any digital circuitry with buffers, as with the clock
tree shown in Figure 7. The gates used in the clock tree must
be capable of operating at frequencies much higher than
those used if added jitter is to be prevented.
20055217
FIGURE 7. Isolating the ADC Clock from other Circuitry
with a Clock Tree
Best performance will be obtained with a differential input
drive, compared with a single-ended drive, as discussed in
Sections 1.3.1 and 1.3.2.
As mentioned in Section 5.0, it is good practice to keep the
ADC clock line as short as possible and to keep it well away
from any other signals. Other signals can introduce jitter into
the clock signal, which can lead to reduced SNR perfor-
mance, and the clock can introduce noise into other lines.
Even lines with 90° crossings have capacitive coupling, so try
to avoid even these 90° crossings of the clock line.
7.0 COMMON APPLICATION PITFALLS
Driving the inputs (analog or digital) beyond the power
supply rails. For proper operation, all inputs should not go
more than 100 mV beyond the supply rails (more than
100 mV below the ground pins or 100 mV above the supply
pins). Exceeding these limits on even a transient basis may
cause faulty or erratic operation. It is not uncommon for high
speed digital components (e.g., 74F devices) to exhibit over-
shoot or undershoot that goes above the power supply or
below ground. A resistor of about 47Ω to 100Ω in series with
any offending digital input, close to the signal source, will
eliminate the problem.
Do not allow input voltages to exceed the supply voltage, even
on a transient basis. Not even during power up or power
down.
Be careful not to overdrive the inputs of the ADC12DL066 with
a device that is powered from supplies outside the range of
the ADC12DL066 supply. Such practice may lead to conver-
sion inaccuracies and even to device damage.
Attempting to drive a high capacitance digital data bus.
The more capacitance the output drivers must charge for
each conversion, the more instantaneous digital current flows
through V_DR and DR GND. These large charging current
spikes can couple into the analog circuitry, degrading dynam-
ic performance. Adequate bypassing and maintaining sepa-
rate analog and digital areas on the pc board will reduce this
problem.
Additionally, bus capacitance beyond the specified 15 pF/pin
will cause t_OD to increase, making it difficult to properly latch
the ADC output data. The result could, again, be an apparent
reduction in dynamic performance.
The digital data outputs should be buffered (with 74AC541,
for example). Dynamic performance can also be improved by
adding series resistors at each digital output, close to the
ADC12DL066, which reduces the energy coupled back into
the converter output pins by limiting the output current. A rea-
sonable value for these resistors is 100Ω.
Using an inadequate amplifier to drive the analog input.
As explained in Section 1.3, the capacitance seen at the input
alternates between 8 pF and 7 pF, depending upon the phase
of the clock. This dynamic load is more difficult to drive than
is a fixed capacitance.
If the amplifier exhibits overshoot, ringing, or any evidence of
instability, even at a very low level, it will degrade perfor-
mance. A small series resistor at each amplifier output and a
capacitor at the analog inputs (as shown in Figure 3 and Fig-
ure 5) will improve performance. The LMH6702 and the
LMH6628 have been successfully used to drive the analog
inputs of the ADC12DL066.
Also, it is important that the signals at the two inputs have
exactly the same amplitude and be exactly 180º out of phase
with each other. Board layout, especially equality of the length
of the two traces to the input pins, will affect the effective
phase between these two signals. Remember that an opera-
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