LP38842-ADJ Datasheet, PDF (2/8 Pages) National Semiconductor (TI) – 1.5A Ultra Low Dropout Adjustable Linear Regulators Stable with Ceramic Output Capacitors

Connection Diagram
PSOP-8, Top View
20117635
Pin Description
Pin Name
BIAS
OUTPUT
GND
INPUT
SHUTDOWN
ADJ
Description
The bias pin is used to provide the low current bias voltage to the chip which operates the internal
circuitry and provides drive voltage for the N-FET.
The regulated output voltage is connected to this pin.
This is both the power and analog ground for the IC. Note that both pin three and the tab of the
TO-220 and TO-263 packages are at ground potential. Pin three and the tab should be tied together
using the PC board copper trace material and connected to circuit ground.
The high current input voltage which is regulated down to the nominal output voltage must be
connected to this pin. Because the bias voltage to operate the chip is provided seperately, the input
voltage can be as low as a few hundered millivolts above the output voltage.
This provides a low power shutdown function which turns the regulated output OFF. Tie to V_BIAS if
this function is not used.
The adjust pin is used to set the regulated output voltage by connecting it to the external resistors R1
and R2 (see Typical Application Circuit).
Ordering Information
Order Number
LP38842MR-ADJ
LP38842MRX-ADJ
Package Type
PSOP-8
PSOP-8
Block Diagram
Package Drawing
MRA08A
MRA08A
Supplied As
95 Units Tape and Reel
2500 Units Tape and Reel
www.national.com
20117624
2